XRT72L50 Datasheet, PDF (49/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
TABLE 1: DESCRIPTION OF MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH THE
INTEL AND MOTOROLA MODES
PIN NAME TYPE
DESCRIPTION
MOTO
I
Selection input for Intel/Motorola Microprocessor Interface.
Setting this pin to a logic "High" configures the Microprocessor Interface to operate in the Motorola
mode. Setting this pin to a logic "Low" configures the Microprocessor Interface to operate in the
Intel Mode.
D[7:0]
I/O Bi-Directional Data Bus for register read or write operations
A[8:0]
I
Nine Bit Address Bus input:
This Nine bit Address Bus is provided to allow the user to select an on-chip register or on-chip
RAM location and select the desired Framer Channel to address.
CS
I
Chip Select input.
This active-low signal selects the Microprocessor Interface of the framer and enables read/write
operations with the on-chip registers/on-chip RAM.
Int
O Interrupt Request Output:
This open-drain/active-low output signal informs the local Microprocessor that the Framer has an
interrupt condition that needs servicing.
RESET
I
Master Reset Input:
Setting this input “Low” resets the internal logic to power-on default settings. This input should be
return to “High” for normal operation.
TABLE 2: DESCRIPTION OF MICROPROCESSOR INTERFACE SIGNALS - OPERATING IN THE INTEL MODE
PIN NAME
EQUIVALENT
PIN IN INTEL
ENVIRONMENT
TYPE
DESCRIPTION
ALE_AS
ALE
I Address-Latch Enable: This active-high signal is used to latch the contents on
the address bus, A[8:0]. The contents of the Address Bus are latched into the
A[8:0] inputs on the falling edge of ALE_AS.
RD_DS
RD
I Read Signal: This active-low input functions as the read signal from the local µP.
When this signal goes "Low", the framer places the contents of the addressed
register on the Data Bus pins (D[7:0]). The Data Bus is tri-stated once this input
signal returns "High".
WR_R/W
WR
I Write Signal: This active-low input functions as the write signal from the local
µP. The contents of the Data Bus (D[7:0]) is written into the addressed register
via A[8:0] on the rising edge of this signal.
RDY_DTCK READY
O Ready Output: This active-low signal is provided by the Framer and indicates
that the current read or write cycle is to be extended until this signal is asserted.
The local µP typically inserts WAIT states until this signal is asserted. This out-
put toggles "Low" when the current read or write cycle is complete.
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