XRT72L50 Datasheet, PDF (382/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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FIGURE 160. THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT OVERHEAD DATA INPUT INTERFACE
(METHOD 2)
34.368M H z
Clock Source
E 3 _ C lo c k _ In
E 3 _ O H _ E n a b le
E3_OH_Out
T x_S tart_o f_F ram e
Insert_O H
T x In C lk
T x O H E n a b le
TxOH
R x L in e C lk
TxO H Fram e
T xO H In s
3 4 .3 6 8 M H z
Clock Source
Term inal Equipm ent
E3 Framer
Method 2 Operation of the Terminal Equipment
If the Terminal Equipment intends to insert any overhead data into the Outbound E3 data stream (via the
Transmit Overhead Data Input Interface), then it is expected to do the following.
1. To sample the state of both the TxOHFrame and the TxOHEnable input signals, via the E3_Clock_In (e.g.,
either the TxInClk or the RxOutClk signal of the XRT72L50) signal. If the Terminal Equipment samples the
TxOHEnable signal "High", then it knows that the XRT72L50 is about to process an overhead bit. Further,
if the Terminal Equipment samples both the TxOHFrame and the TxOHEnable pins "High" (at the same
time) then the Terminal Equipment knows that the XRT72L50 is about to process the first overhead bit,
within a new E3 frame.
2. To keep track of the number of times that the TxOHEnable signal has been sampled "High" since the last
time both the TxOHFrame and the TxOHEnable signals were sampled "High". By doing this, the Terminal
Equipment will be able to keep track of which overhead bit the Transmit Overhead Data Input Interface is
about ready to process. From this, the Terminal Equipment will know when it should assert the TxOHIns
input pin and place the appropriate value on the TxOH input pins of the XRT72L50.
Table 72 also relates the number of TxOHEnable output pulses (that have occurred since both the TxOHFrame
and TxOHEnable pins were sampled "High") to the E3 overhead bit, that is being processed.
TABLE 72: THE RELATIONSHIP BETWEEN THE NUMBER OF TXOHENABLE PULSES (SINCE THE LAST OCCURRENCE OF
THE TXOHFRAME PULSE) TO THE E3 OVERHEAD BIT, THAT IS BEING PROCESSED BY THE XRT72L50
NUMBER OF TXOHENABLE PULSES
THE OVERHEAD BIT EXPECTED BY THE CAN THIS OVERHEAD BIT BE ACCEPTED BY
XRT72L50
THE XRT72L50?
0 (Clock edge is coincident with TxO-
FA1 Byte - Bit 7
No
HFrame being detected "High")
1
FA1 Byte - Bit 6
No
2
FA1 Byte - Bit 5
No
3
FA1 Byte - Bit 4
No
4
FA1 Byte - Bit 3
No
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