XRT72L50 Datasheet, PDF (198/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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Transmit DS3 FEAC Configuration & Status Register (Address = 0x31)
BIT 7
RO
0
BIT 6
Not Used
RO
0
BIT 5
RO
0
BIT 4
Tx FEAC
Interrupt
Enable
R/W
1
BIT 3
TxFEAC
Interrupt
Status
RUR
1
BIT 2
TxFEAC
Enable
R/W
0
BIT 1
TxFEAC
GO
R/W
0
BIT 0
TxFEAC
Busy
RO
0
The purpose of this interrupt is to alert the Microcontroller/Microprocessor that the Transmit FEAC Processor
has completed its transmission of a given FEAC message and is now ready to transmit the next FEAC
Message, to the Remote Terminal Equipment.
4.2.6.1.3
The Completion of Transmission of the LAPD Message Interrupt
If the Transmit Section interrupts have been enabled at the Block level, then the Completion of Transmission of
a LAPD Message Interrupt can be enabled or disabled by writing the appropriate value into Bit 1 (TxLAPD
Interrupt Enable) within the Tx DS3 LAPD Status & Interrupt Register (Address = 0x34), as illustrated below.
TxDS3 LAPD Status and Interrupt Register (Address = 0x34)
BIT 7
RO
0
BIT 6
BIT 5
Not Used
RO
RO
0
0
BIT 4
RO
0
BIT 3
TxDL Start
BIT 2
TxDL Busy
R/W
RO
0
0
BIT 1
TxLAPD
Interrupt
Enable
R/W
0
BIT 0
TxLAPD
Interrupt
Status
RUR
0
Setting this bit-field to “1’ enables the Completion of Transmission of a LAPD Message Interrupt. Conversely,
setting this bit-field to “0” disables the Completion of Transmission of a LAPD Message interrupt.
4.2.6.1.4
Servicing the Completion of Transmission of a LAPD Message Interrupt
As mentioned previously, once the user commands the LAPD Transmitter to begin its transmission of a LAPD
Message, it will do the following.
1. It will compute the FCS (Frame Check Sequence) value over the contents of 0x86 through 0xDB and
append this 16 bit value to the back-end of the user-message.
2. It will parse through the contents of the Transmit LAPD Message Buffer (located at address locations 0x86
through 0xDB and the FCS bytes) and search for a string of five (5) consecutive “1’s”. If the LAPD Trans-
mitter finds a string of five consecutive “1’s” (within the content of the LAPD Message Buffer, then it will
insert a “0” immediately after this string. (Except at 0x86 which should contain the flag sequence byte
0x7E.)
3. It will append a trailing flag sequence byte, 0x7E.
4. Finally, it will begin transmitting the contents of this LAPD Message frame via the DL bits, within each out-
bound DS3 frame.
5. Once the LAPD Transmitter has completed its transmission of this LAPD Message frame (to the Remote
Terminal Equipment), the XRT72L50 Framer IC will generate the Completion of Transmission of a LAPD
Message Interrupt to the Microcontroller/Microprocessor. Once the XRT72L50 Framer IC generates this
interrupt, it will do the following.
• Assert the Interrupt Output pin (Int) by toggling it "Low".
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