XRT72L50 Datasheet, PDF (238/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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FIGURE 84. AN ILLUSTRATION OF THE BEHAVIOR OF THE SIGNALS BETWEEN THE RECEIVE PAYLOAD DATA OUTPUT
INTERFACE BLOCK OF THE XRT72L50 AND THE TERMINAL EQUIPMENT (NIBBLE-MODE OPERATION).
Terminal Equipment Signals
RxOutClk
Rx_DS3_Clock_In
DS3_Data_In[3:0]
Rx_Start_of_Frame
Nibble [0]
XRT72L5x Receive Payload Data I/F Signals
RxOutClk
RxClk
RxNib[3:0]
RxFrame
Nibble [0]
DS3 Frame Number N
Note: RxFrame pulses high to denote
DS3 Frame Boundary.
DS3 Frame Number N + 1
Recommended Sampling Edge of Terminal
Equipment
Nibble [1]
Nibble [1]
4.3.6 Receive Section Interrupt Processing
The Receive Section of the XRT72L50 can generate an interrupt to the Microcontroller/Microprocessor for the
following reasons.
• Change of State of Receive LOS (Loss of Signal) condition
• Change of State of Receive OOF (Out of Frame) condition
• Change of State of Receive AIS (Alarm Indicator Signal) condition
• Change of State of Receive Idle Condition.
• Change of State of Receive FERF (Far-End Receive Failure) condition.
• Change of State of AIC (Application Identification Channel) bit.
• Detection of P-Bit Error in a DS3 frame
• Detection of CP-Bit Error in a DS3 frame
• The Receive FEAC Message - Validation Interrupt
• The Receive FEAC Message - Removal Interrupt
• Completion of Reception of a LAPD Message
4.3.6.1 Enabling Receive Section Interrupts
The Interrupt Structure, within the XRT72L50 contains two hierarchical levels.
• Block Level
• Source Level
The Block Level
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