XRT72L50 Datasheet, PDF (247/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
• Conversely, if the AIC bit-field is “1”, then the user should configure the XRT72L50 Framer IC to operate in
the C-bit Parity framing format.
4.3.6.2.7
The Detection of P-Bit Error Interrupt
If the Detection of P-Bit Error Interrupt is enabled, then the XRT72L50 Framer IC will generate an interrupt,
anytime the Receive DS3 Framer block has detected a P-bit error, within the incoming DS3 data stream.
Enabling and Disabling the Detection of P-Bit Error Interrupt:
The Detection of P-Bit Error Interrupt can be enabled or disabled by writing the appropriate value into Bit 0 (P-
Bit Error Interrupt Enable) within the RxDS3 Interrupt Enable Register, as illustrated below.
RxDS3 Interrupt Enable Register (Address = 0x12)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CP Bit Error
Interrupt
Enable
LOS
Interrupt
Enable
AIS
Interrupt
Enable
Idle Interrupt
Enable
FERF
Interrupt
Enable
AIC
Interrupt
Enable
OOF
Interrupt
Enable
P-Bit Error
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Setting this bit-field to “1” enables this interrupt. Conversely, setting this bit-field to “0” disables this interrupt.
Servicing the Detection of P-Bit Error Interrupt
Whenever the XRT72L50 Framer IC detects this interrupt, it will do all of the following.
• It will assert the Interrupt Request output pin (Int) by driving it "High".
• It will set Bit 0 (P-Bit Error Interrupt Status) within the Rx DS3 Interrupt Status Register, to “1”, as indicated
below.
RxDS3 Interrupt Status Register (Address = 0x13)
BIT 7
CP-Bit Error
Interrupt
Status
RUR
0
BIT 6
LOS
Interrupt
Status
RUR
0
BIT 5
AIS
Interrupt
Status
RUR
0
BIT 4
Idle Interrupt
Status
RUR
0
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
AIC
Interrupt
Status
RUR
0
BIT 1
OOF
Interrupt
Status
RUR
0
BIT 0
P-Bit Error
Interrupt
Status
RUR
1
Whenever the Terminal Equipment encounters the Detection of P-bit Error Interrupt, It should read the contents
of PMON Parity Error Count Register (located at 0x54 and 0x55), in order to determine the number of P-bit
errors recently received.
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