XRT72L50 Datasheet, PDF (452/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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6.3.6.2.2
The Change in Receive OOF Condition Interrupt
If the Change in Receive OOF Condition Interrupt is enabled, then the XRT72L50 Framer IC will generate an
interrupt in response to either of the following conditions.
1. When the XRT72L50 Framer IC declares an OOF (Out of Frame) Condition, and
2. When the XRT72L50 Framer IC clears the OOF condition.
Conditions causing the XRT72L50 Framer IC to declare an OOF Condition.
• If the Receive E3 Framer block (within the XRT72L50 Framer IC) detects Framing Byte errors, within four
consecutive incoming E3 frames.
Conditions causing the XRT72L50 Framer IC to clear the OOF Condition.
• If the Receive E3 Framer block (within the XRT72L50 Framer IC) transitions from the FA1, FA2 Octet
Verification state to the In-Frame state (see Figure 182).
• If the Receive E3 Framer block transitions from the OOF Condition state to the In-Frame state (see
Figure 182).
Enabling and Disabling the Change in Receive OOF Condition Interrupt
The user can enable or disable the Change in Receive OOF Condition Interrupt, by writing the appropriate
value into Bit 3 (OOF Interrupt Enable), within the RxE3 Interrupt Enable Register - 1, as indicated below.
RxE3 Interrupt Enable Register - 1 (Address = 0x12)
BIT 7
BIT 6
Not Used
BIT 5
RO
RO
RO
0
0
0
BIT 4
COFA
Interrupt
Enable
R/W
0
BIT 3
OOF
Interrupt
Enable
R/W
0
BIT 2
LOF
Interrupt
Enable
R/W
0
BIT 1
LOS
Interrupt
Enable
R/W
X
BIT 0
AIS
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables this interrupt. Conversely, setting this bit-field to “0” disables this interrupt.
Servicing the Change in Receive OOF Condition Interrupt
Whenever the XRT72L50 Framer IC detects this interrupt, it will do all of the following.
• It will assert the Interrupt Request output pin (Int), by driving it "Low".
• It will set Bit 3 (OOF Interrupt Status), within the Rx E3 Interrupt Status Register - 1 to “1”, as indicated below.
RxE3 Interrupt Status Register - 1 (Address = 0x14)
BIT 7
BIT 6
Not Used
BIT 5
RO
RO
RO
0
0
0
BIT 4
COFA
Interrupt
Status
RUR
0
BIT 3
OOF
Interrupt
Status
RUR
1
BIT 2
LOF
Interrupt
Status
RUR
0
BIT 1
LOS
Interrupt
Status
RUR
0
BIT 0
AIS
Interrupt
Status
RUR
0
Whenever the user’s system encounters the Change in Receive OOF Condition Interrupt, then it should do the
following.
1. It should determine the current state of the OOF condition. Recall, that this interrupt can be generated,
whenever the XRT72L50 Framer IC declares or clears the OOF defect. Hence, the user can determine the
current state of the LOS defect by reading the state of Bit 5 (RxOOF) within the Rx E3 Configuration and
Status Register - 2, as illustrated below.
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