XRT72L50 Datasheet, PDF (418/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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detects an error in the Frame Alignment bytes, it will increment the PMON Framing Error Event Count
Registers (Address = 0x52 and 0x53). The bit-format for these two registers are depicted below.
PMON Framing Bit/Byte Error Count Register - MSB (Address = 0x52)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Framing Bit/Byte Error Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
BIT 1
RUR
0
BIT 0
RUR
0
PMON Framing Bit/Byte Error Count Register - LSB (Address = 0x53)
BIT 7
RUR
0
BIT 6
RUR
0
BIT 5
BIT 4
BIT 3
BIT 2
Framing Bit/Byte Error Count - Low Byte
RUR
RUR
RUR
RUR
0
0
0
0
BIT 1
RUR
0
BIT 0
RUR
0
6.3.2.3 Forcing a Reframe via Software Command
The XRT72L50 Framer IC permits the user to command a reframe procedure with the Receive E3 Framer
block via software command. If the user writes a “1” into Bit 0 (Reframe) within the I/O Control Register
(Address = 0x01), as depicted below, then the Receive E3 Framer block will be forced into the FA1, FA2 Octet
Search state, per Figure 182, and will begin its search for the FA1 and FA2 octets.)
I/O CONTROL REGISTER (ADDRESS = 0X01)
BIT 7
Disable
TxLOC
R/W
1
BIT 6
LOC
RO
0
BIT 5
Disable
RxLOC
R/W
1
BIT 4
AMI/
ZeroSup*
BIT 3
Unipolar/
Bipolar*
R/W
R/W
0
0
BIT 2
TxLine
Clk
Invert
R/W
0
BIT 1
RxLine
Clk
Invert
R/W
0
BIT 0
Reframe
R/W
1
The Framer IC will respond to this command by doing the following.
1. Asserting both the RxOOF and RxLOF output pins.
2. Generating both the Change in OOF Status and the Change in LOF Status interrupts to the Microproces-
sor.
3. Asserting both the RxLOF and RxOOF bit-fields within the Rx E3 Configuration & Status Register, as
depicted below.
RxE3 Configuration & Status Register 2 (Address = 0x11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Rx LOF Algo RxLOF
RxOOF
RxLOS
RxAIS
RxPld Unstab
Rx
TMark
RxFERF
R/W
RO
RO
RO
RO
RO
RO
RO
0
1
1
1
1
1
1
1
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