XRT72L50 Datasheet, PDF (241/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
1. It should cease transmitting a FERF indicator to the Remote Terminal Equipment. The XRT72L50 Framer
IC automatically supports this action via the FERF-upon-LOS feature.
2. It should transmit the appropriate FEAC Message (per Bellcore GR-499-CORE), to the Remote Terminal
Equipment, indicating that the Loss of Signal condition has been cleared.
4.3.6.2.2
The Change of State on Receive OOF Interrupt
If the Change of State on Receive OOF (Out-of-Frame) Interrupt is enabled, then the XRT72L50 Framer IC will
generate an interrupt in response to either of the following conditions.
1. When the XRT72L50 Framer IC declares an OOF (Out of Frame) condition, and
2. When the XRT72L50 Framer IC clears the OOF (Out of Frame) condition.
Conditions causing the XRT72L50 Framer IC to declare an OOF condition
• If the Receive DS3 Framer block (within the XRT72L50 Framer IC) detects at least either 3 or 6 F-bit errors,
in the last 16 F-bits.
Conditions causing the XRT72L50 Framer IC to clear the OOF condition.
• Whenever, the Receive DS3 Framer block transitions from the M-Bit Search into the In-Frame state (within
the Frame Acquisition/Maintenance State Machine Diagram).
Enabling and Disabling the Change of State on Receive OOF Interrupt:
The Change of State on Receive OOF Interrupt can be enabled or disabled by writing the appropriate value
into Bit 1 (OOF Interrupt Enable) within the RxDS3 Interrupt Enable Register, as illustrated below.
RxDS3 Interrupt Enable Register (Address = 0x12)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CP Bit Error
Interrupt
Enable
LOS
Interrupt
Enable
AIS
Interrupt
Enable
Idle Interrupt
Enable
FERF
Interrupt
Enable
AIC
Interrupt
Enable
OOF
Interrupt
Enable
P-Bit Error
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Setting this bit-field to “1” enables this interrupt. Conversely, setting this bit-field to “0” disables this interrupt.
Servicing the Change of State on Receive OOF Interrupt
Whenever the XRT72L50 Framer IC detects this interrupt, it will do all of the following.
• It will assert the Interrupt Request output pin (Int) by driving this pin "Low".
• It will set Bit 1 (OOF Interrupt Status), within the RxDS3 Interrupt Status Register to “1”, as indicated below.
RxDS3 Interrupt Status Register (Address = 0x13)
BIT 7
CP-Bit Error
Interrupt
Status
RUR
0
BIT 6
LOS
Interrupt
Status
RUR
0
BIT 5
AIS
Interrupt
Status
RUR
0
BIT 4
Idle Interrupt
Status
RUR
0
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
AIC
Interrupt
Status
RUR
0
BIT 1
OOF
Interrupt
Status
RUR
1
BIT 0
P-Bit Error
Interrupt
Status
RUR
0
Whenever the Terminal Equipment encounters a Change in OOF on Receive Interrupt, then it should do the
following.
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