XRT72L50 Datasheet, PDF (375/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
TABLE 68: A LISTING OF THE OVERHEAD BITS WITHIN THE E3 FRAME, AND THEIR POTENTIAL SOURCES, WITHIN THE
XRT72L50 IC
OVERHEAD BIT
INTERNALLY GENERATED
ACCESSIBLE VIA THE TRANSMIT OVERHEAD
DATA INPUT INTERFACE
BUFFER/REGISTER
ACCESSIBLE
TR - Bit 0
No
Yes
Yes
MA - Bit 7
Yes
Yes
Yes
MA - Bit 6
Yes
Yes
Yes
MA - Bit 5
Yes
Yes
Yes
MA - Bit 4
Yes
Yes
Yes
MA - Bit 3
Yes
Yes
Yes
MA - Bit 2
Yes
Yes
Yes
MA - Bit 1
Yes
Yes
Yes
MA - Bit 0
Yes
Yes
Yes
NR - Bit 7
No
Yes
Yes
NR - Bit 6
No
Yes
Yes
NR - Bit 5
No
Yes
Yes
NR - Bit 4
No
Yes
Yes
NR - Bit 3
No
Yes
Yes
NR - Bit 2
No
Yes
Yes
NR - Bit 1
No
Yes
Yes
NR - Bit 0
No
Yes
Yes
GC - Bit 7
No
Yes
Yes
GC - Bit 6
No
Yes
Yes
GC - Bit 5
No
Yes
Yes
GC - Bit 4
No
Yes
Yes
GC - Bit 3
No
Yes
Yes
GC - Bit 2
No
Yes
Yes
GC - Bit 1
No
Yes
Yes
GC - Bit 0
No
Yes
Yes
NOTES:
1. The XRT72L50 contains mask register bits that permit the user to alter the state of the internally generated value
for these bits.
2. The Transmit LAPD Controller/Buffer can be configured to be the source of the NR or GC bytes, within the
Outbound E3 data stream.
In all, the Transmit Overhead Data Input Interface permits the user to insert overhead data into the Outbound
E3 frames via the following two different methods.
• Method 1 - Using the TxOHClk clock signal
• Method 2 - Using the TxInClk and the TxOHEnable signals.
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