XRT72L50 Datasheet, PDF (363/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
FIGURE 148. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT72L50 AND THE TERMINAL
EQUIPMENT (MODE 2 OPERATION)
Term inal Equipm ent Signals
E 3 _ C lo c k _ In
E 3_D ata_O u t
Tx_S tart_of_F ram e
E 3_O v erhead _Ind
Payload[4238] Payload[4239] FA1, Bit 7
FA1, Bit 6
XRT72L5x Transm it Payload Data I/F Signals
T xIn C lk
TxSer
Payload[4238] Payload[4239]
TxFram eR ef
TxO H _ In d
FA1, Bit 7
FA1, Bit 6
E3 Frame Number N
E3 Frame Number N + 1
Note: The FA1 byte will not be processed by the
Note: TxOH_Ind pulses high for 16 bit periods in order to
Transmit Payload Data Input Interface.
denote Overhead Data (e.g., the FA1 and FA2
bytes)
Note: TxFrameRef pulses high to denote
E3 Frame Boundary.
How to configure the XRT72L50 to operate in this mode.
1. Set the NibIntf input pin "Low".
2. Set the TimRefSel[1:0] bit-fields (within the Framer Operating Mode Register) to "01" as depicted below.
Framer Operating Mode Register (Address = 0x00)
BIT 7
Local Loop-back
BIT 6
DS3/E3*
R/W
R/W
0
0
BIT 5
Internal LOS
Enable
R/W
1
BIT 4
RESET
R/W
0
BIT 3
Interrupt
Enable Reset
R/W
1
BIT2
Frame Format
R/W
1
BIT 1
BIT 0
TimRefSel[1:0]
R/W
R/W
0
1
3. Interface the XRT72L50, to the Terminal Equipment, as illustrated in Figure 147.
6.2.1.3 Mode 3 - The Serial/Local-Timed/Frame-Master ModeBehavior of the XRT72L50
If the XRT72L50 has been configured to operate in this mode, then the XRT72L50 will function as follows.
A. Local Timed - Uses the TxInClk signal as the Timing Reference
In this mode, the Transmit Section of the XRT72L50 will use the TxInClk signal as its timing reference.
B. Serial Mode
The XRT72L50 will receive the E3 payload data, in a serial manner, via the TxSer input pin. The Transmit
Payload Data Input Interface (within the XRT72L50) will latch this data into its circuitry, on the rising edge of the
TxInClk input clock signal.
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