XRT72L50 Datasheet, PDF (270/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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the TxNibClk output pin. The Transmit Terminal Equipment Input Interface block (within the XRT72L50) will
use the rising edge of the TxNibClk signal, to latch the data, residing on the TxNib[3:0] into its circuitry.
B. Nibble-Parallel Mode
The XRT72L50 will accept the E3 payload data, from the Terminal Equipment, in a parallel manner, via the
TxNib[3:0] input pins. The Transmit Terminal Equipment Input Interface will latch this data into its circuitry, on
the rising edge of the TxNibClk output signal.
C. Delineation of outbound E3 Frames
The Transmit Section will use the TxInClk input signal as its timing reference and will initiate the generation of
E3 frames, asynchronous with respect to any external signal. The XRT72L50 will pulse the TxFrame output
pin "High" whenever it is processing the last bit, within a given outbound E3 frame.
D. Sampling of payload data, from the Terminal Equipment
In Mode 6, the XRT72L50 will sample the data, at the TxNib[3:0] input pins, on the third rising edge of the
TxInClk clock signal, following a pulse in the TxNibClk signal (see Figure 99).
NOTE: The TxNibClk signal, from the XRT72L50 operates nominally at 8.592 MHz (e.g., 34.368 MHz divided by 4).
Interfacing the Transmit Payload Data Input Interface block of the XRT72L50 to the Terminal Equipment
for Mode 6 Operation
Figure 98 presents an illustration of the Transmit Payload Data Input Interface block (within the XRT72L50)
being interfaced to the Terminal Equipment, for Mode 6 Operation.
FIGURE 98. THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE
BLOCK FOR MODE 6 (NIBBLE-PARALLEL/LOCAL-TIMED/FRAME-MASTER) OPERATION
E3_Nib_Clock_In
E3_Data_Out[3:0]
Tx_Start_of_Frame
E3_Overhead_Ind
34.368MHz
Clock Source
8.592MHz
4
TxInClk
TxNibClk
NibIntf
TxNib[3:0]
VCC
TxNibFrame
TxOH_Ind
Terminal Equipment
E3 Framer
Mode 6 Operation of the Terminal Equipment
In Figure 98 both the Terminal Equipment and the XRT72L50 will be driven by an external 8.592MHz clock
signal. The Terminal Equipment will receive the 8.592MHz clock signal via the E3_Nib_Clock_In input pin.
The XRT72L50 will output the 8.592MHz clock signal via the TxNibClk output pin.
The Terminal Equipment will serially output the data on the E3_Data_Out[3:0] pins upon the rising edge of the
signal at the E3_Clock_In input pin. The XRT72L50 will latch the data, residing on the TxNib[3:0] input pins, on
the rising edge of the TxNibClk signal.
In this case the XRT72L50 has the responsibility of providing the framing reference signal by pulsing the
TxFrame output pin (and in turn the Tx_Start_of_Frame input pin of the Terminal Equipment) "High" for one bit-
period, coincident with the last bit within a given E3 frame.
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