XRT72L50 Datasheet, PDF (428/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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The user can determine the total number of FEBE Events (e.g., E3 frames that have been received with the
FEBE bit-field set to “1”) that have occurred since the last read of this register. This register is reset-upon-read.
6.3.2.9 Receiving the Trail Trace Buffer Messages
The XRT72L50 Framer IC contains 16 bytes worth of Transmit Trail Trace Buffers, and 16 bytes worth of
Receive Trail Trace Buffers, as described below. The role of the Transmit Trail Trace Buffers are described in
Section 6.1.1.3 and Section 6.2.4.2.2.
The XRT72L50 DS3/E3 Framer IC contains 16 Receive Trail Trace Buffer registers (e.g., RxTTB-0 through
RxTTB-15). The purpose of these registers are to receive and store the incoming Trail Access Point Identifier
from the Remote Transmitting Terminal.
The Local Receiving Terminal will use this information to verify that it is still receiving data from its intended
transmitter. The specific use of these registers follows.
For Trail Trace Buffer purposes, the Remote Transmit E3 Framer block will group 16 consecutive E3 frames into
a Trail Trace Buffer super-frame. When the Remote Transmit E3 Framer is generating the first E3 frame, within
a Trail Trace Buffer super-frame, it will insert the value [1, C6, C5, C4, C3, C2, C1, C0], into the TR byte-field of
this Outbound E3 frame. The remaining 15 TR byte-fields (within this Trail Trace Buffer super-frame) will
consists of ASCII characters that are required for the E.164 numbering format.
When the Local Receive E3 Framer block receives an E3 frame, containing a value in the TR byte that has a
“1” in the MSB position, then it (the Receive E3 Framer block) will write this value into the RxTTB-0 Register
(Address = 0x1C). Once this occurs, the Receive E3 Framer block will notify the Microprocessor of this new
incoming Trail Trace Buffer message by generating the Change in Trail Trace Buffer Message interrupt. The
Receive E3 Framer block will also set bit 6 (TTB Change Interrupt Status) within the Rx E3 Framer Interrupt
Status Register - 2, as depicted below.
RxE3 Interrupt Status Register - 2 (Address = 0x15)
BIT 7
Not Used
RO
0
BIT 6
TTB
Change
Interrupt
Status
RUR
1
BIT 5
Not Used
BIT 4
FEBE
Interrupt
Status
RO
RUR
0
0
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
BIT 1
BIP-8
Error Interrupt
Status
Framing
Byte Error
Interrupt
Status
RUR
RUR
0
0
BIT 0
RxPld
Mis
Interrupt
Status
RUR
0
The contents of the TR byte-field, in the very next E3 frame will be written into the Rx TTB-1 Register (Address
= 0x1D), and so on until all 16 bytes have been received.
NOTES:
1. Anytime the Receive E3 Framer block receives an E3 frame that contains an octet in the TR byte-field, with a “1” in
the MSB (Most Significant Bit) position, then the Receive E3 Framer block will (1) write the contents of the TR
byte-field (in this E3 frame) into the RxTTB-0 Register,
2. It will generate the Change in Trail Trace Buffer Interrupt. The Receive E3 Framer will do these things independent
of the number of E3 frames that have been received since the last occurrence of the Change in Trail Trace Buffer
Interrupt. Hence, the user, when writing data into the Tx TTB registers, must take care to insure that only the Tx
TTB-0 register contains an octet with a “1” in the MSB position. All remaining Tx TTB registers (e.g., TxTTB-1
through TxTTB-15) must contain octets with a “0” in the MSB position.
3. The Framer IC will not verify the CRC-7 value that is written into the Rx TTB-0” register. It is up to the user’s
system hardware and/or software to perform this verification.
6.3.3 The Receive HDLC Controller Block
The Receive E3 HDLC Controller block can be used to receive message-oriented signaling (MOS) type data
link messages from the remote terminal equipment.
The MOS types of HDLC message processing is discussed in detail below.
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