XRT72L50 Datasheet, PDF (23/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PIN DESCRIPTION
PIN #
58
PIN NAME
TxNibFrame/
ValFCS
59
TxNibClk/
SndFCS
60
GND
61
TxFrame
62
VDD
63
TxLineClk
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. 1.2.1
TYPE
O
O
I
****
O
****
O
DESCRIPTION
Transmit Frame Boundary Indicator - Nibble/Parallel Interface:
This output pin pulses "High" when the last nibble of a given DS3 or E3 frame
is expected at the TxNib[3:0] input pins.
The purpose of this output pin is to alert the Terminal Equipment that it needs
to begin transmission of a new DS3 or E3 frame to the XRT72L50.
Valid Frame Check Sequence:
When the HDLC is on, this pin will go "High" at the end of a valid Frame
Check Sequence.
Transmit Nibble Clock Signal:
If the user opts to operate the XRT72L50 in the Nibble-Parallel mode,
then the XRT72L50 will derive this clock signal from either the TxInClk
or the RxLineClk signal (depending upon which signal is selected as
the timing reference).
The user is advised to configure the Terminal Equipment to output the
outbound payload data (to the XRT72L50 Framer IC) onto the Tx-
Nib[3:0] input pins, upon the rising edge of this clock signal.
NOTES:
1. For DS3 applications, the XRT72L50 Framer IC will output 1176 clock
edges (to the Terminal Equipment) for each outbound DS3 frame.
2. For E3, ITU-T G.832 applications, the XRT72L50 Framer IC will out-
put 1074 clock edges (to the Terminal Equipment) for each outbound
E3 frame.
3. For E3, ITU-T G.751 applications, the XRT72L50 Framer IC will out-
put 384 clock edges (fo the Terminal Equipment) for each outbound
E3 frame.
Send Frame Check Sequence:
When the HDLC controller is turned on, this pin is driven "High" during the
time when FCS bytes are being sent after a valid HDLC message.
Ground
Transmit End of DS3 or E3 Frame Indicator:
The Transmit Section of the XRT72l50 will pulse this output pin "High" (for one
bit-period), when the Transmit Payload Data Input Interface is processing the
last bit of a given DS3 or E3 frame.
The purpose of this output pin is to alert the Terminal Equipment that it needs
to begin transmission of a new DS3 or E3 frame to the XRT72l50 (e.g., to per-
mit the XRT72l50 to maintain Transmit DS3/E3 framing alignment control over
the Terminal Equipment).
Power Supply 3.3V + 5%
Transmit Line Interface Clock:
This clock signal is output to the Line Interface Framer, along with the TxPOS
and TxNEG signals. The purpose of this output clock signal is to provide the
LIU with timing information that it can use to generate the AMI pulses and
deliver them over the transmission medium to the Far-End Receiver. The user
can configure the source of this clock to be either the RxLineClk (from the
Receiver portion of the Framer) or the TxInClk input. The nominal frequency
of this clock signal is 34.368 MHz.
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