XRT72L50 Datasheet, PDF (134/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
áç
Block Interrupt Status Register (Address = 0x05)
BIT 7
RxDS3/E3
Interrupt
Status
RO
0
BIT 6
RO
0
BIT 5
BIT 4
Not Used
BIT 3
RO
RO
RO
0
0
0
BIT 2
RO
0
BIT 1
TxDS3/E3
Interrupt
Status
BIT 0
One-Second
Interrupt
Status
RO
RUR
0
1
The Block Interrupt Status Register presents the interrupt request status of each functional block, within the
chip. The purpose of the Block Interrupt Status Register is to help the local µP/µC identify which functional
block(s) within a given channel has requested the interrupt. Whichever bit(s) are asserted in this register,
identifies which block(s) have experienced an interrupt-generating condition as presented in Table 5. Once the
local µP/µC has read this register, it can determine which branch within the interrupt service routine that it must
follow, in order to properly service this interrupt.
The Framer further supports the Functional Block hierarchy by providing the Block Interrupt Enable Register
(Address = 0x04). The bit format of this register is identical to that for the Block Interrupt Status register, and is
presented below for the sake of completeness.
Block Interrupt Enable Register (Address = 0x04)
BIT 7
RxDS3/E3
Interrupt
Enable
R/W
0
BIT 6
RO
0
BIT 5
BIT 4
Not Used
BIT 3
RO
RO
RO
0
0
0
BIT 2
RO
0
BIT 1
TxDS3/E3
Interrupt
Enable
BIT 0
One-Second
Interrupt
Enable
R/W
R/W
0
0
The Block Interrupt Enable register allows the user to individually enable or disable the interrupt requesting
capability of the functional blocks. If a particular bit-field, within this register contains the value "0", then the
corresponding functional block has been disabled from generating any interrupt requests. Conversely, if that
bit-field contains the value "1", then the corresponding functional block has been enabled for interrupt
generation (e.g., those potential interrupts, within the enabled functional block that are enabled at the source
level, are now enabled). The user should be aware of the fact that each functional block contains anywhere
from 1 to 12 potential interrupt sources. Each of these lower level interrupt sources contain their own set of
interrupt enable bits and interrupt status bits, existing in various on-chip registers.
Interrupt Service Routing Branching: after reading the Block Interrupt Status Register.
The contents of the Block Interrupt Status Register identify which of 3 functional blocks has requested interrupt
service. The local µP should use this information in order to determine where, within the Interrupt Service
Routing, program control should branch to. Table 9 can be viewed as an interrupt service routine guide. It lists
each of the Functional Blocks, that contain a bit-field in the Block Interrupt Status Register. Additionally, this
table also presents a list and addresses of corresponding on-chip Registers that the Interrupt Service Routine
should branch to and read, based upon the Interrupting Functional Block.
Table 9, Table 10, and Table 11 presents the Interrupt Service Routine guide for DS3, E3/ITU-T G.832 and E3/
ITU-T G.751 applications, respectively.
121