XRT72L50 Datasheet, PDF (22/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. 1.2.1
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PIN DESCRIPTION
PIN #
54
PIN NAME
TxOH/
TxHDLCDat5
55
TxOHInd/
TxHDLCDat6
56
TxOHEnable/
TxHDLCDat7
57
TxOHFrame/
TxHDLCClk
TYPE
I
O
I
O
I
O
DESCRIPTION
Transmit Overhead Input Pin:
The Transmit Overhead Data Input Interface accepts the overhead data via
this input pin, and inserts into the overhead bit position within the very next
outbound DS3 or E3 frame. If the TxOHIns pin is pulled "High", the Transmit
Overhead Data Input Interface will sample the data at this input pin (TxOH),
on the falling edge of the TxOHClk output pin. Conversely, if the TxOHIns pin
is pulled "Low", then the Transmit Overhead Data Input Interface will NOT
sample the data at this input pin (TxOH). Consequently, this data will be
ignored.
Transmit HDLC Data Input - 5:
This pin accepts bit 5 TxHDLC data when the HDLC controller is turned on.
Transmit Overhead Data Indicator:
This output pin will pulse "High" one-bit period prior to the time that the Trans-
mit Section of the XRT72L50 will be processing an Overhead bit. The pur-
pose of this output pin is to warn the Terminal Equipment that, during the very
next bit-period, the XRT72L50 is going to be processing an Overhead bit and
will be ignoring any data that is applied to the TxSer input pin.
NOTE: For DS3 applications, this output pin is only active if the XRT72L50 is
operating in the Serial Mode. This output pin will be pulled "Low" if the device
is operating in the Nibble-Parallel Mode.
Transmit HDLC Data Input - 6:
This pin accepts bit 6 TxHDLC data when the HDLC controller is turned on.
Transmit Overhead Input Enable:
The XRT72L50 will assert this signal, for one TxInClk period, just prior to the
instant that the Transmit Overhead Data Input Interface will be sampling and
processing an overhead bit.
If the Terminal Equipment intends to insert its own value for an overhead bit,
into the outbound DS3 or E3 frame, it is expected to sample the state of this
signal, upon the falling edge of TxInClk. Upon sampling the TxOHEnable
"High", the Terminal Equipment should (1) place the desired value of the over-
head bit, onto the TxOH input pin and (2) assert the TxOHIns input pin. The
Transmit Overhead Data Input Interface” block will sample and latch the data
on the TxOH signal, upon the rising edge of the very next TxInClk input sig-
nal.
Transmit HDLC Data Input - 7:
This pin accepts bit 7 TxHDLC data when the HDLC controller is turned on.
Transmit Overhead Framing Pulse:
This output pin pulses "High" when the Transmit Overhead Data Input Inter-
face block is expecting the first Overhead bit, within a DS3 or E3 frame to be
applied to the TxOH input pin.
This pin is "High" for one clock period of TxOHClk.
Transmit HDLC Output Clock:
When the HDLC controller is on, TxHDLCDat is updated by the 72L53 by this
clock signal.
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