XRT72L50 Datasheet, PDF (366/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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A. Looped Timing (Uses the RxLineClk as the Timing Reference)
In this mode, the Transmit Section of the XRT72L50 will use the RxLineClk signal as its timing reference.
When the XRT72L50 is operating in the Nibble-Mode, it will internally divide the RxLineClk signal, by a factor of
four (4) and will output this signal via the TxNibClk output pin.
B. Nibble-Parallel Mode
The XRT72L50 will accept the E3 payload data, from the Terminal Equipment in a nibble-parallel manner, via
the TxNib[3:0] input pins. The Transmit Terminal Equipment Input Interface block will latch this data into its
circuitry, on the rising edge of the TxNibClk output signal.
C. Delineation of the Outbound E3 frames
The XRT72L50 will pulse the TxNibFrame output pin "High" for one bit-period, coincident with the XRT72L50
processing the last nibble of a given E3 frame.
D. Sampling of payload data, from the Terminal Equipment
In Mode 4, the XRT72L50 will sample the data, at the TxNib[3:0] input pins, on the third rising edge of the
RxOutClk clock signal, following a pulse in the TxNibClk signal (see Figure 152).
NOTE: The TxNibClk signal, from the XRT72L50, operates nominally at 8.592 MHz (e.g., 34.368 MHz divided by 4).
The E3 Frame consists of 537 bytes or 1074 nibbles. Therefore, the XRT72L50 will supply 1074 TxNibClk
pulses between the rising edges of two consecutive TxNibFrame pulses. The E3 Frame repetition rate is
8.0kHz. Hence, 1074 TxNibClk pulses for each E3 frame period amounts to TxNibClk running at
approximately 8.592 MHz.
Nominally, the Transmit Section within the XRT72L50 will generate a TxNibClk pulse for every 4 RxOutClk (or
TxInClk) periods.
Interfacing the Transmit Payload Data Input Interface block of the XRT72L50 to the Terminal Equipment
for Mode 4 Operation
Figure 151 presents an illustration of the Transmit Payload Data Input Interface block (within the XRT72L50)
being interfaced to the Terminal Equipment, for Mode 4 Operation.
FIGURE 151. THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE
BLOCK FOR MODE 4 (NIBBLE-PARALLEL/LOOP-TIMED) OPERATION
E3_Nib_Clock_In
E3_Data_Out[3:0]
Tx_Start_of_Frame
E3_Overhead_Ind
8.592MHz
4
VCC
TxNibClk
TxNib[3:0]
TxNibFrame
RxLineClk
TxOH_Ind
NibIntf
34.368MHz
Terminal Equipment
E3 Framer
Mode 4 Operation of the Terminal Equipment
When the XRT72L50 is operating in this mode, it will function as the source of the 8.592MHz (e.g., the
34.368MHz clock signal divided by 4) clock signal that will be used as the Terminal Equipment Interface clock
by both the XRT72L50 and the Terminal Equipment.
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