XRT72L50 Datasheet, PDF (205/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
FIGURE 67. WAVEFORM/TIMING RELATIONSHIP BETWEEN RXLINECLK, RXPOS AND RXNEG - WHEN RXPOS AND
RXNEG ARE TO BE SAMPLED ON THE FALLING EDGE OF RXLINECLK
t₄₂
RxLineClk
t₄₀
t₄₁
RxPOS
RxNEG
4.3.2 The Receive DS3 Framer Block
The Receive DS3 Framer block accepts decoded DS3 data from the Receive DS3 LIU Interface block, and
routes data to the following destinations.
• The Receive Payload Data Output Interface Block
• The Receive Overhead Data Output Interface Block.
• The Receive DS3 HDLC Controller Block
Figure 68 presents a simple illustration of the Receive DS3 Framer block along with the associated paths to the
other functional blocks within the Framer chip.
FIGURE 68. THE RECEIVE DS3 FRAMER BLOCK AND THE ASSOCIATED PATHS TO OTHER FUNCTIONAL BLOCKS
To Receive DS3 HDLC
Buffer
Receive Overhead Data
Output Interface
Receive Payload Data
Output Interface
Receive
DS3
Framer Block
From Receive DS3
LIU Interface Block
Once the B3ZS (or AMI) encoded data has been decoded into a binary data-stream, the Receive DS3 Framer
block will use portions of this data-stream in order to synchronize itself to the remote terminal equipment. At
any given time, the Receive DS3 Framer block will be operating in one of two modes.
• The Frame Acquisition Mode: In this mode, the Receive DS3 Framer block is trying to acquire
synchronization with the incoming DS3 frames, or
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