XRT72L50 Datasheet, PDF (10/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. 1.2.1
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Figure 98. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 6 (Nibble-
Parallel/Local-Timed/Frame-Master) Operation ........................................................................................... 257
Figure 99. Behavior of the Terminal Interface signals between the XRT72L50 and the Terminal Equipment (E3 Mode 6
Operation) .................................................................................................................................................... 258
5.2.2 The Transmit Overhead Data Input Interface ........................................................................................ 259
Figure 100. The Transmit Overhead Data Input Interface block .................................................................................. 259
5.2.2.1 Method 1 - Using the TxOHClk Clock Signal .............................................................................. 260
TABLE 44: A LISTING OF THE OVERHEAD BITS WITHIN THE E3 FRAME, AND THEIR POTENTIAL SOURCES, WITHIN THE XRT72L50 IC
260
TABLE 45: DESCRIPTION OF METHOD 1 TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS ............................................... 261
Figure 101. The Terminal Equipment being interfaced to the Transmit Overhead Data Input Interface (Method 1) ... 262
TABLE 46: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN TXOHCLK, (SINCE TXOHFRAME WAS LAST
SAMPLED "HIGH") TO THE E3 OVERHEAD BIT, THAT IS BEING PROCESSED ........................................................ 263
Figure 102. Illustration of the signal that must occur between the Terminal Equipment and the XRT72L50 in order to
configure the XRT72L50 to transmit a Yellow Alarm to the remote terminal equipment .............................. 264
5.2.2.2 Method 2 - Using the TxInClk and TxOHEnable Signals ............................................................ 265
TABLE 47: DESCRIPTION OF METHOD 2 TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS ............................................... 265
Figure 103. The Terminal Equipment being interfaced to the Transmit Overhead Data Input Interface (Method 2) ... 266
TABLE 48: THE RELATIONSHIP BETWEEN THE NUMBER OF TXOHENABLE PULSES (SINCE THE LAST OCCURRENCE OF THE
TXOHFRAME PULSE) TO THE E3 OVERHEAD BIT, THAT IS BEING PROCESSED BY THE XRT72L50 ..................... 267
5.2.3 The Transmit E3 HDLC Controller ......................................................................................................... 268
5.2.3.1 Message-Oriented Signaling (e.g., LAP-D) processing via the Transmit E3 HDLC Controller ... 268
Figure 104. Behavior of Transmit Overhead Data Input Interface signals between the XRT72L50 and the Terminal Equipment
(for Method 2) .............................................................................................................................................. 268
Figure 105. LAPD Message Frame Format ................................................................................................................ 269
TABLE 49: THE LAPD MESSAGE TYPE AND THE CORRESPONDING VALUE OF THE FIRST BYTE, WITHIN THE INFORMATION PAYLOAD
270
TABLE 50: RELATIONSHIP BETWEEN TXLAPD MSG LENGTH AND THE LAPD MESSAGE SIZE ............................................ 271
Figure 106. Flow Chart Depicting how to use the LAPD Transmitter .......................................................................... 274
5.2.4 The Transmit E3 Framer Block .............................................................................................................. 275
5.2.4.1 Brief Description of the Transmit E3 Framer ............................................................................... 275
5.2.4.2 Detailed Functional Description of the Transmit E3 Framer Block .............................................. 276
Figure 107. The Transmit E3 Framer Block and the associated paths to other Functional Blocks ............................. 277
TABLE 51: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TX AIS ENABLE) WITHIN THE TX E3 CONFIGURATION REGISTER,
AND THE RESULTING TRANSMIT E3 FRAMER BLOCK'S ACTION .......................................................................... 278
TABLE 52: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (TX LOS) WITHIN THE TX E3 CONFIGURATION REGISTER, AND THE
RESULTING TRANSMIT E3 FRAMER BLOCK'S ACTION ........................................................................................ 278
5.2.5 The Transmit E3 Line Interface Block ................................................................................................... 281
Figure 108. Interfacing the XRT72L50 Framer IC to the XRT73L00 DS3/E3/STS-1 LIU ............................................ 282
Figure 109. The Transmit E3 LIU Interface block ........................................................................................................ 282
5.2.5.1 Selecting the various Line Codes ................................................................................................ 283
Figure 110. The Behavior of TxPOS and TxNEG signals during data transmission while the Transmit E3 LIU Interface is
operating in the Unipolar Mode .................................................................................................................... 283
TABLE 53: THE RELATIONSHIP BETWEEN THE CONTENT OF BIT 3 (UNIPOLAR/BIPOLAR) WITHIN THE UNI I/O CONTROL REGISTER
AND THE TRANSMIT E3 FRAMER LINE INTERFACE OUTPUT MODE ..................................................................... 284
Figure 111. Illustration of AMI Line Code .................................................................................................................... 284
5.2.5.2 TxLineClk Clock Edge Selection ................................................................................................. 285
Figure 112. Illustration of two examples of HDB3 Encoding ....................................................................................... 285
TABLE 54: THE RELATIONSHIP BETWEEN BIT 4 (AMI/HDB3*) WITHIN THE I/O CONTROL REGISTER AND THE BIPOLAR LINE CODE
THAT IS OUTPUT BY THE TRANSMIT E3 LIU INTERFACE BLOCK ......................................................................... 285
TABLE 55: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL REGISTER AND THE
TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ............................................................ 286
Figure 113. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG are configured to
be updated on the rising edge of TxLineClk ................................................................................................ 286
5.2.6 Transmit Section Interrupt Processing .................................................................................................. 287
5.2.6.1 Enabling Transmit Section Interrupts .......................................................................................... 287
Figure 114. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG are configured to
be updated on the falling edge of TxLineClk ............................................................................................... 287
5.3 THE RECEIVE SECTION OF THE XRT72L50 (E3 MODE OPERATION) .................................................................... 289
Figure 115. The XRT72L50 Receive Section configured to operate in the E3 Mode ................................................. 289
5.3.1 The Receive E3 LIU Interface Block ...................................................................................................... 290
5.3.1.1 Unipolar Decoding ....................................................................................................................... 290
Figure 116. The Receive E3 LIU Interface Block ........................................................................................................ 290
5.3.1.2 Bipolar Decoding ......................................................................................................................... 291
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