XRT72L50 Datasheet, PDF (165/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
• The X bits
• The FEAC bits
• The FEBE bits.
The Data Link Related Overhead Bits
The DS3 frame structure also contains bits which can be used to transport User Data Link information and
Path Maintenance Data Link information. The UDL (User Data Link) bits are only accessible via the Transmit
Overhead Data Input Interface. The Path Maintenance Data Link (PMDL) bits can either be sourced from the
Transmit LAPD Controller/Buffer or via the Transmit Overhead Data Input Interface.
Table 16 lists the Overhead Bits within the DS3 frame. This table also indicates whether or not these overhead
bits can be sourced by the Transmit Overhead Data Input Interface.
TABLE 16: OVERHEAD BITS WITHIN THE DS3 FRAME AND THEIR POTENTIAL SOURCES WITHIN THE XRT72L50 IC
OVERHEAD BIT
INTERNALLY GENERATED
ACCESSIBLE VIA THE TRANSMIT OVERHEAD
DATA INPUT INTERFACE
BUFFER/REGISTER
ACCESSIBLE
P
Yes
No
Yes*
X
Yes
Yes
Yes*
F
Yes
No
Yes*
M
Yes
No
Yes*
FEAC
No
Yes
Yes
FEBE
Yes
Yes
Yes
DL
No
Yes
Yes+
UDL
No
Yes
No
CP
Yes
Yes
No
* The XRT72L50 contains mask register bits that permit the altering to fhe state of the internally generated value for these
bits.
+ The Transmit LAPD Controller/Buffer can be configured to be the source of the DL bits within the outbound DS3 data
stream.
In all, the Transmit Overhead Data Input Interface permits the insertion of overhead data into the outbound DS3
frames via the following methods:
• Method 1 - Using the TxOHClk clock signal
• Method 2 - Using the TxInClk and the TxOHEnable signals.
4.2.2.1 Method 1 - Using the TxOHClk Clock Signal
The Transmit Overhead Data Input Interface consists of five signals. Of these five signals, the following four
signals are to be used when implementing Method 1.
• TxOH
• TxOHClk
• TxOHFrame
• TxOHIns
Each of these signals are listed and described in Table 17.
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