XRT72L50 Datasheet, PDF (120/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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NOTE: This register is ignored if Bit 7 (Tx BIP-4 Enable) within the TxE3 Configuration register (Address = 0x30) is set to
“0”.
2.3.8 Performance Monitor Registers
2.3.8.1 PMON Line Code Violation Count Register - MSB
PMON LCV Event Count Register - MSB (Address = 0x50)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LCV Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
This Reset-upon-Read register, along with the PMON LCV Event Count Register - LSB (Address = 0x51)
contains a 16-bit representation of the number of Line Code Violations that have been detected by the Receive
DS3/E3 Framer block, since the last read of these registers. This register contains the MSB (or Upper-Byte)
value of this 16 bit expression.
2.3.8.2 PMON Line Code Violation Count Register - LSB
PMON LCV Event Count Register - LSB (Address = 0x51)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LCV Count - Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
This Reset-upon-Read register, along with the PMON LCV Event Count Register - LSB (Address = 0x50)
contains a 16-bit representation of the number of Line Code Violations that have been detected by the Receive
DS3/E3 Framer block, since the last read of these registers. This register contains the LSB (or Lower-Byte)
value of this 16 bit expression.
2.3.8.3 PMON Framing Bit/Byte Error Count Register - MSB
PMON Framing Bit/Byte Error Count Register - MSB (Address = 0x52)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Framing Bit/Byte Error Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
This Reset-upon-Read register, along with the PMON Framing Bit/Byte Error Count Register - LSB (Address =
0x53) contains a 16-bit representation of the number of Framing Bit or Byte Errors that have been detected by
the Receive DS3/E3 Framer block, since the last read of these registers. This register contains the MSB (or
Upper-Byte) value of this 16 bit expression.
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