XRT72L50 Datasheet, PDF (322/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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RxE3 Interrupt Status Register - 2 (Address = 0x15)
BIT 7
RO
0
BIT 6
BIT 5
Not Used
RO
RO
0
0
BIT 4
RO
0
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
BIP-4
Error
Interrupt
Status
RUR
1
BIT 1
Framing
Error
Interrupt
Status
RUR
0
BIT 0
Not Used
RUR
0
Finally, the Receive E3 Framer block will increment the PMON Parity Error Count registers. The byte format of
these registers are presented below.
PMON Parity Error Count Register - MSB (Address = 0x54)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Parity Error Count - High Byte
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
PMON Parity Error Count Register - LSB (Address = 0x55)
BIT 7
RUR
0
BIT 6
RUR
0
BIT 5
RUR
0
BIT 4
BIT 3
Parity Error Count - Low Byte
RUR
RUR
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
The user can determine the number of BIP-4 Errors that have been detected by the Receive E3 Framer block,
since the last read of these registers. These registers are reset-upon-read.
Configuring the XRT72L50 Framer IC to support BIP-4 Error Detection
In order to perform BIP-4 checking of each E3 frame, the user must configure the XRT72L50 Framer IC
accordingly, by executing the following steps.
1. Configure the Transmit Section (of the XRT72L50 Framer IC) to insert the BIP-4 value into the outbound
E3 frames. This is accomplished by writing a “1” into bit-field 7 (Tx BIP-4 Enable) within the TxE3 Configu-
ration Register, as illustrated below.
TxE3 Configuration Register (Address = 0x30)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Tx
BIP-4
Enable
TxASourceSel[1:0]
TxNSourceSel[1:0]
R/W
R/W
R/W
R/W
R/W
1
0
0
0
0
BIT 2
Tx AIS
Enable
R/W
0
BIT 1
Tx LOS
Enable
R/W
0
BIT 0
Tx FAS
Source
Select
R/W
0
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