XRT72L50 Datasheet, PDF (465/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
HDLC Control Register (Address = 0x82)
BIT 7
Framer
By-Pass
R/W
0
BIT 6
HDLC
ON
R/W
1
BIT 5
CRC-32
Select
R/W
0
BIT 4
Reserved
R/W
0
BIT 3
HDLC
Loop-Back
R/W
0
BIT 2
R/W
0
BIT 1
Reserved
R/W
0
BIT 0
R/W
0
8.2 Operating the High Speed HDLC Controller
Once the user has configured the XT72L50 to operate in the High-Speed HDLC Controller Mode, then both the
Transmit and Receive HDLC Controller blocks will be active.
8.2.1 Operating the Transmit HDLC Controller Block
Once the XRT72L50 has been configured to operate in the High-Speed HDLC Controller mode, then certain
pins, which have multiple functions, are configured to support operation of the Transmit and Receive HDLC
Controller blocks.
The Transmit HDLC Controller block within the XRT72L50 consists of the following pins
TABLE 89: DESCRIPTION OF EACH OF THE TRANSMIT HDLC CONTROLLER PIN
PIN NAME
Snd_Msg
Snd_FCS
TYPE
DESCRIPTION
I ^{Send Message Command:}
This input pin permits the user to command the Transmit HDLC Controller block to begin
sampling and latching the data which is being applied to the TxHDLCDat[7:0] input pins.
If the user pulls this input pin "High", then the Transmit HDLC Controller block samples and
latches the data which is applied to the TxHDLCDat[7:0] input pins upon the rising edge of
TxHDLCClk. Each byte of this sampled data will ultimately be encapsulated into an out-
bound HDLC Frame.
If the user pulls this input pin "Low", then the Transmit HDLC Controller block will simply gen-
erate a constant stream of Flag Sequence octets (0x7E).
I ^{Send Frame Check Sequence Command:}
The user’s terminal equipment is expected to control both this input pin and the Snd_Msg
input pin during the construction and transmission of each outbound HDLC frame.
This input pin permits the user to command the Transmit HDLC Controller block to compute
and insert the compute FCS value into the back-end of the outbound HDLC frame as a trailer.
If the user has configured the Transmit HDLC Controller to compute and insert a CRC-16
value into the outbound HDLC frame, then the terminal equipment is expected to pull this
input pin "High" for two periods of TxHDLCClk.
If the user has configured the Transmit HDLC Controller to compute and insert a CRC-32
value into the outbound HDLC frame, then the terminal equipment is expected to pull this
input pin "High" for four periods of TxHDLCClk.
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