XRT72L50 Datasheet, PDF (448/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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FIGURE 198. THE XRT72L50 DS3/E3 FRAMER IC BEING INTERFACED TO THE RECEIVE SECTION OF THE TERMINAL
EQUIPMENT (NIBBLE-PARALLEL MODE OPERATION)
Rx_E3_Clock_In
E3_Data_In[3:0]
Rx_Start_of_Frame
Rx_E3_OH_Ind
8.592MHz
Clock Signal
RxClk
RxNib[3:0]
RxLineClk
RxFrame
34.368MHz
Clock Source
RxOH_Ind
Terminal Equipment
Receive Payload Section
E3 Framer
Required Operation of the Terminal Equipment
The XRT72L50 will update the data on the RxNib[3:0] line, upon the rising edge of RxClk. Hence, the Terminal
Equipment should sample the data on the RxNib[3:0] output pins (or the E3_Data_In[3:0] input pins at the
Terminal Equipment) upon the rising edge of RxClk. As the Terminal Equipment samples RxSer with each
rising edge of RxClk it should also be sampling the RxFrame signal.
The Need for Sampling RxFrame
The XRT72L50 will pulse the RxFrame output pin "High" coincident with it driving the very first nibble of a given
E3 frame, onto the RxNib[3:0] output pins. If knowledge of the E3 Frame Boundaries is important for the
operation of the Terminal Equipment, then this is a very important signal for it to sample.
The Behavior of the Signals between the Receive Payload Data Output Interface block and the Terminal
Equipment
The behavior of the signals between the XRT72L50 and the Terminal Equipment for E3 Nibble-Mode operation
is illustrated in Figure 199.
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