XRT72L50 Datasheet, PDF (52/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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7. After some settling time, the data on the bi-directional data bus will stabilize and can be read by the µC/µP.
The XRT72L50 DS3/E3 Framer will indicate that this data can be read by toggling the RDY_DTCK
(READY) signal "Low".
8. After the µC/µP detects the RDY_DTCK signal, it can then terminate the Read Cycle by toggling the
RD_DS (Read Strobe) input pin "High".
Figure 23 presents a timing diagram which illustrates the behavior of the Microprocessor Interface signals
during an Intel-type Programmed I/O Read Operation.
FIGURE 23. MICROPROCESSOR INTERFACE TIMING - INTEL-TYPE PROGRAMMED I/O READ OPERATION
ALE_AS
A [8 :0 ]
CS
D [7 :0 ]
RD_DS
W R_R/W
RDY_DTCK
Address of Target Register
Not Valid
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The Intel Mode Write Cycle
Whenever an Intel-type µC/µP wishes to write a byte or word of data into a register or buffer location, it should
do the following.
1. Place the address of the target register or buffer location on the Address Bus input pins, A[8:0].
2. While the µC/µP is placing this address value onto the Address Bus, the Address Decoding circuitry (within
the user's system) should assert the CS input pin of the Framer by toggling it "Low". This enables further
communication between the µC/µP and the Framer Microprocessor Interface block.
3. Assert the ALE_AS input pin by toggling it "High". When the µC/µP asserts the ALE_AS input pin, it
enables the Address Bus Input Drivers within the Framer chip.
4. After allowing the data on the Address Bus pins to settle (by waiting the appropriate Address Setup time),
the µC/µP should toggle the ALE_AS input pin "Low". This step causes the Framer to latch the contents of
the Address Bus into its internal circuitry. At this point, the address of the register or buffer location has
now been selected.
5. The µC/µP should then place the byte or word that it intends to write into the target register, on the bi-direc-
tional data bus, D[7:0].
6. Next, the µC/µP should indicate that this current bus cycle is a Write Operation by toggling the WR_R/W
(Write Strobe) input pin "Low". This action also enables the bi-directional data bus input drivers of the
Framer.
7. After some amount of time when the data on the bi-directional data bus to settles, the RDY will go “low indi-
cating that data has been written to its destination, the µC/µP will toggle the WR_R/W (Write Strobe) input
pin "High", which terminates the write cycle.
8. Figure 24 presents a timing diagram which illustrates the behavior of the Microprocessor Interface signals
during an Intel-type Programmed I/O Write Operation.
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