XRT72L50 Datasheet, PDF (419/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
6.3.2.4
Performance Monitoring of the Frame Synchronization Section, within the Receive E3
Framer block
The user can monitor the number of framing bytes (FA1 and FA2 bytes) errors that have been detected by the
Receive E3 Framer block. This is accomplished by periodically reading the PMON Framing Bit/Byte Error
Event Count Registers (Address = 0x52 and 0x53). The byte format of these registers are presented in
Section 6.3.2.2.
6.3.2.5 The RxOOF and RxLOF output pin.
The user can roughly determine the current framing state that the Receive E3 Framer block is operating in by
reading the logic state of the RxOOF and the RxLOF output pins. Table 82 presents the relationship between
the state of the RxOOF and RxLOF output pins, and the Framing State of the Receive E3 Framer block.
TABLE 82: THE RELATIONSHIP BETWEEN THE LOGIC STATE OF THE RXOOF AND RXLOF OUTPUT PINS, AND THE
FRAMING STATE OF THE RECEIVE E3 FRAMER BLOCK
RXLOF
0
0
1
1
RXOOF
FRAMING STATE OF THE RECEIVE E3 FRAMER BLOCK
0 In Frame
1 OOF Condition (The Receive E3 Framer block is operating in the 3ms OOF period).
0 Invalid
1 LOF Condition
6.3.2.6 E3 Receive Alarms
6.3.2.6.1
The Loss of Signal (LOS) Alarm
Declaring an LOS Condition
The Receive E3 Framer block will declare a Loss of Signal (LOS) Condition, when it detects 32 consecutive
incoming “0’s” via the RxPOS and RxNEG input pins or if the ExtLOS input pin (from the XRT73L00 DS3/E3/
STS-1 LIU IC) is asserted. In this case, the internally-generated LOS criteria of 180 consecutive “zeros” will be
disabled. This can be accomplished by writing a "0" to bit 5 (Internal LOS Enable) of the Framer Operating
Mode Register, as depicted below.
Framer Operating Mode Register (Address = 0x00)
BIT 7
BIT 6
BIT 5
Local Loop-back DS3/E3 Internal LOS
Enable
R/W
R/W
R/W
X
1
0
BIT 4
RESET
R/W
X
BIT 3
Interrupt
Enable Reset
R/W
X
BIT2
Frame Format
R/W
X
The Receive E3 Framer block will indicate that it is declaring an LOS condition by.
• Asserting the RxLOS output pin (e.g., toggling it "High").
BIT 1
BIT 0
TimRefSel[1:0]
R/W
R/W
X
X
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