XRT72L50 Datasheet, PDF (379/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
TABLE 70: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN TXOHCLK, (SINCE
"TXOHFRAME" WAS LAST SAMPLED "HIGH") TO THE E3 OVERHEAD BIT, THAT IS BEING PROCESSED
NUMBER OF RISING CLOCK EDGES IN
TXOHCLK
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
THE OVERHEAD BIT EXPECTED BY THE CAN THIS OVERHEAD BIT BE ACCEPTED BY
"XRT72L50"
THE XRT72L50?
TR Byte - Bit 1
Yes
TR Byte - Bit 0
Yes
MA Byte - Bit 7
Yes (FERF Bit)
MA Byte - Bit 6
Yes (FEBE Bit)
MA Byte - Bit 5
Yes
MA Byte - Bit 4
Yes
MA Byte - Bit 3
Yes
MA Byte - Bit 2
Yes
MA Byte - Bit 1
Yes
MA Byte - Bit 0
Yes
NR Byte - Bit 7
Yes
NR Byte - Bit 6
Yes
NR Byte - Bit 5
Yes
NR Byte - Bit 4
Yes
NR Byte - Bit 3
Yes
NR Byte - Bit 2
Yes
NR Byte - Bit 1
Yes
NR Byte - Bit 0
Yes
GC Byte - Bit 7
Yes
GC Byte - Bit 6
Yes
GC Byte - Bit 5
Yes
GC Byte - Bit 4
Yes
GC Byte - Bit 3
Yes
GC Byte - Bit 2
Yes
GC Byte - Bit 1
Yes
GC Byte - Bit 0
Yes
3. After the Terminal Equipment has waited the appropriate number of clock edges (from the TxOHFrame sig-
nal being sampled "High"), it should assert the TxOHIns input signal. Concurrently, the Terminal Equip-
ment should also place the appropriate value (of the inserted overhead bit) onto the TxOH signal.
4. The Terminal Equipment should hold both the TxOHIns input pin "High" and the value of the TxOH signal,
stable until the next rising edge of TxOHClk is detected.
366