XRT72L50 Datasheet, PDF (468/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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Once the outbound HDLC frame has been formed, then it will be transmitted to the remote terminal equipment
via payload bits of the outbound DS3 or E3 frames.
If the user’s terminal equipment does not supply any more data which needs to be encapsulated into the
outbound HDLC frame and transmitted to the remote terminal equipment, then the Transmit HDLC Controller
block begins transmitting a constant stream of flag sequence octets (0x7E). These flag sequence octets will
also be transmitted to the remote terminal equipment via the payload bits of the outbound DS3 or E3 frames.
8.2.2 Operating the Receive HDLC Controller Block
The Receive HDLC Controller block within the XRT72L50 consists of the following pins:
TABLE 90: DESCRIPTION OF EACH OF THE RECEIVE HDLC CONTROLLER PINS
PIN NAME
RxIdle
Val_FCS
RxHDLCClk
RxHDLCData[7:0]
TYPE
DESCRIPTION
O ^{Receive Idle (Flag Sequence) Indicator Signal}
The combination of the RxIdle and Val_FCS output signals are used to convey information
about data that is being received via the Receive HDLC Controller block.
If RxIdle = "High":
The Receive HDLC Controller block pulses this output pin "High" any time the flag
sequence is present on the RxHDLCDat[7:0] output data bus.
If RxIdle and Val_FCS are both "High":
The Receive HDLC Controller block has received a complete HDLC frame and has deter-
mined that the FCS value within this HDLC frame is valid.
If RxIdle is "High" and Val_FCS is "Low":
The Receive HDLC Controller block has received a complete HDLC frame and has deter-
mined that the FCS value within this HDLC frame is invalid.
If RxIdle is "Low" and Val_FCS is "High":
The Receive HDLC Controller block has received an ABORT sequence.
O ^{Valid FCS Indicator Signal}
Please see description above.
O ^{Receive HDLC Controller Clock Output signal:}
The Receive HDLC Controller block outputs data via the RxHDLCDat[7:0] output pins
upon the rising edge of this clock signal. The user is advised to configure the terminal
equipment circuitry to sample the contents of the RxHDLCDat[7:0] output pins upon the
falling edge of this clock signal.
I ^{Receive HDLC Controller - Output Data Bus:}
The Receive HDLC Controller block outputs data via these output pins upon the rising
edge of the RxHDLCClk clock signal. The user is advised to configure the terminal equi-
ment circuitry to sample the contents of this data bus upon the falling edge of this clock
signal.
8.2.2.1 Receive Payload HDLC Processor
The receiver HDLC processor is the counter part of the transmit HDLC processor for formatting the payload
portion of the receive DS3/E3 data that is activated when the HDLCon bit in the HDLC Control register (0x82)
is set.
This receiver performs idle flag detection, stuffed zero removal, and FCS checking on the incoming data
stream. The recovered data bytes are presented on RxHDLCData[7:0] and are valid on the rising edge of
RxHDLCClk . The LSB is on RxHDLCData[0] and the MSB on RxHDLCData[7]; the LSB is the first received
from the serial input. User should sample RxHDLCData on falling edge of RxHDLCClk.
If the payload stream contains idle flags, the IDLE pin will be high and the flags will be present on
RxHDLCData[7:0]. If a valid FCS is received at the end of the message block, the ValidFCS pin will be active
high while RxIDLE is high. At the start of the next message, both indications will go low until the end of the
incoming message has been received. If a bad FCS is received, RxIDLE will go high and ValidFCS will remain
low. If ValidFCS goes high and RxIDLE does not, an abort sequence was received in the data. If there is only
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