PIC24FJ64GA705 Datasheet, PDF (99/412 Pages) –

PIC24FJ256GA705 FAMILY
TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode
Oscillator Source POSCMD<1:0>
FNOSC<2:0>
Notes
Oscillator with Frequency Division
Internal/External
11
(OSCFDIV)
111
1, 2, 3
Low-Power RC Oscillator (LPRC)
Internal
11
101
3
Secondary (Timer1) Oscillator
Secondary
11
(SOSC)
100
3
Primary Oscillator (XT) with PLL
Primary
01
011
Module (XTPLL)
Primary Oscillator (EC) with PLL
Primary
00
011
Module (ECPLL)
Primary Oscillator (HS)
Primary
10
010
Primary Oscillator (XT)
Primary
01
010
Primary Oscillator (EC)
Primary
00
010
Fast RC Oscillator with PLL Module
Internal
11
(FRCPLL)
001
3
Fast RC Oscillator (FRC)
Internal
11
000
3
Note 1: The input oscillator to the OSCFDIV Clock mode is determined by the RCDIV<2:0> (CLKDIV<10:8) bits.
At POR, the default value selects the FRC module.
2: This is the default Oscillator mode for an unprogrammed (erased) device.
3: OSCO pin function is determined by the OSCIOFCN Configuration bit.
9.3 Control Registers
The operation of the oscillator is controlled by five
Special Function Registers:
• OSCCON
• CLKDIV
• OSCTUN
• OSCDIV
• OSCFDIV
The OSCCON register (Register 9-1) is the main con-
trol register for the oscillator. It controls clock source
switching and allows the monitoring of clock sources.
OSCCON is protected by a write lock to prevent
inadvertent clock switches. See Section 9.4 “Clock
Switching Operation” for more information.
The CLKDIV register (Register 9-2) controls the
features associated with Doze mode, as well as the
postscalers for the OSCFDIV Clock mode and the PLL
module.
The OSCTUN register (Register 9-3) allows the user to
fine-tune the FRC Oscillator over a range of
approximately ±1.5%.
The OSCDIV and OSCFDIV registers provide control
for the system oscillator frequency divider.
 2016 Microchip Technology Inc.
DS30010118B-page 99