PIC24FJ64GA705 Datasheet, PDF (277/412 Pages) –

PIC24FJ256GA705 FAMILY
23.0 CONFIGURABLE LOGIC CELL
(CLC) GENERATOR
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to
the “dsPIC33/PIC24 Family Reference
Manual”, “Configurable Logic Cell (CLC)”
(DS33949), which is available from the
Microchip web site (www.microchip.com).
The information in this data sheet
supersedes the information in the FRM.
The Configurable Logic Cell (CLC) module allows the
user to specify combinations of signals as inputs to a
logic function and to use the logic output to control
other peripherals or I/O pins. This provides greater
flexibility and potential in embedded designs, since the
CLC module can operate outside the limitations of
software execution and supports a vast amount of
output designs.
There are four input gates to the selected logic func-
tion. These four input gates select from a pool of up to
32 signals that are selected using four data source
selection multiplexers. Figure 23-1 shows an overview
of the module. Figure 23-3 shows the details of the data
source multiplexers and logic input gate connections.
FIGURE 23-1:
CLCx MODULE
CLCIN[0]
CLCIN[1]
CLCIN[2]
CLCIN[3]
CLCIN[4]
CLCIN[5]
CLCIN[6]
CLCIN[7]
CLCIN[8]
CLCIN[9]
CLCIN[10]
CLCIN[11]
CLCIN[12]
CLCIN[13]
CLCIN[14]
CLCIN[15]
CLCIN[16]
CLCIN[17]
CLCIN[18]
CLCIN[19]
CLCIN[20]
CLCIN[21]
CLCIN[22]
CLCIN[23]
CLCIN[24]
CLCIN[25]
CLCIN[26]
CLCIN[27]
CLCIN[28]
CLCIN[29]
CLCIN[30]
CLCIN[31]
See Figure 23-2
Gate 1
Gate 2
Gate 3
Gate 4
LCEN
Logic
Function
Logic
Output
MODE<2:0>
See Figure 23-3
LCPOL
CLCx
Output
Interrupt
det
INTP
INTN
Interrupt
det
Note: All register bits shown in this figure can be found in the CLCxCONL register.
LCOE
TRISx Control
CLCx
Sets
CLCxIF
Flag
 2016 Microchip Technology Inc.
DS30010118B-page 277