PIC24FJ64GA705 Datasheet, PDF (194/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 16-3: CCPxCON2L: CCPx CONTROL 2 LOW REGISTERS
R/W-0
R/W-0
U-0
R/W-0
U-0
U-0
PWMRSEN ASDGM
—
SSDG
—
—
bit 15
R/W-0
ASDG7
bit 7
R/W-0
ASDG6
R/W-0
ASDG5
R/W-0
ASDG4
R/W-0
ASDG3
R/W-0
ASDG2
U-0
—
R/W-0
ASDG1
U-0
—
bit 8
R/W-0
ASDG0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11-8
bit 7-0
PWMRSEN: CCPx PWM Restart Enable bit
1 = ASEVT bit clears automatically at the beginning of the next PWM period, after the shutdown input
has ended
0 = ASEVT bit must be cleared in software to resume PWM activity on output pins
ASDGM: CCPx Auto-Shutdown Gate Mode Enable bit
1 = Waits until the next Time Base Reset or rollover for shutdown to occur
0 = Shutdown event occurs immediately
Unimplemented: Read as ‘0’
SSDG: CCPx Software Shutdown/Gate Control bit
1 = Manually forces auto-shutdown, timer clock gate or input capture signal gate event (setting of
ASDGM bit still applies)
0 = Normal module operation
Unimplemented: Read as ‘0’
ASDG<7:0>: CCPx Auto-Shutdown/Gating Source Enable bits
1 = ASDGx Source n is enabled (see Table 16-6 for auto-shutdown/gating sources)
0 = ASDGx Source n is disabled
TABLE 16-6: AUTO-SHUTDOWN SOURCES
ASDG<7:0>
MCCP1
Auto-Shutdown Source
MCCP2
MCCP3
1xxx xxxx
x1xx xxxx
xx1x xxxx
xxx1 xxxx
xxxx 1xxx
xxxx x1xx
xxxx xx1x
xxxx xxx1
CLC1
CLC2
OCFB
OCFA
Not Used
Not Used
CMP3 Out
CMP2 Out
CMP1 Out
Not Used
MCCP4
DS30010118B-page 194
 2016 Microchip Technology Inc.