PIC24FJ64GA705 Datasheet, PDF (289/412 Pages) –

PIC24FJ256GA705 FAMILY
24.2 Extended DMA Operations
In addition to the standard features available on all 12-bit
A/D Converters, PIC24FJ256GA705 family devices
implement a limited extension of DMA functionality.
This extension adds features that work with the
device’s DMA Controller to expand the A/D module’s
data storage abilities beyond the module’s built-in
buffer.
The Extended DMA functionality is controlled by the
DMAEN bit (AD1CON1<11>); setting this bit enables
the functionality. The DMABM bit (AD1CON1<12>)
configures how the DMA feature operates.
24.2.1 EXTENDED BUFFER MODE
Extended Buffer mode (DMABM = 1) maps the A/D
Data Buffer registers and data from all channels above
13 into a user-specified area of data RAM. This allows
users to read the conversion results of channels above
13, which do not have their own memory-mapped A/D
buffer locations, from data memory.
To accomplish this, the DMA must be configured in
Peripheral Indirect Addressing mode and the DMA
destination address must point to the beginning of the
buffer. The DMA count must be set to generate an
interrupt after the desired number of conversions.
In Extended Buffer mode, the A/D control bits will function
similarly to non-DMA modes. The BUFREGEN bit will still
select between FIFO mode and Channel-Aligned mode,
but the number of words in the destination FIFO will be
determined by the SMPI<4:0> bits in DMA mode. In FIFO
mode, the BUFM bit will still split the output FIFO into two
sets of 13 results (the SMPIx bits should be set accord-
ingly) and the BUFS bit will still indicate which set of
results is being written to and which can be read.
24.2.2 PIA MODE
When DMABM = 0, the A/D module is configured to
function with the DMA Controller for Peripheral Indirect
Addressing (PIA) mode operations. In this mode, the
A/D module generates an 11-bit Indirect Address (IA).
This is ORed with the destination address in the DMA
Controller to define where the A/D conversion data will
be stored.
In PIA mode, the buffer space is created as a series of
contiguous smaller buffers, one per analog channel.
The size of the channel buffer determines how many
analog channels can be accommodated. The size of
the buffer is selected by the DMABL<2:0> bits
(AD1CON4<2:0>). The size options range from a
single word per buffer to 128 words. Each channel is
allocated a buffer of this size, regardless of whether or
not the channel will actually have conversion data.
The IA is created by combining the base address within
a channel buffer with three to five bits (depending on
the buffer size) to identify the channel. The base
address ranges from zero to seven bits wide, depend-
ing on the buffer size. The address is right-padded with
a ‘0’ in order to maintain address alignment in the Data
Space. The concatenated channel and base address
bits are then left-padded with zeros, as necessary, to
complete the 11-bit IA.
The IA is configured to auto-increment which channel
is written in each analog input’s sub-buffer during write
operations by using the SMPIx bits (AD1CON2<6:2>).
As with PIA operations for any DMA-enabled module,
the base destination address in the DMADSTn register
must be masked properly to accommodate the IA.
Table 24-1 shows how complete addresses are
formed. Note that the address masking varies for each
buffer size option. Because of masking requirements,
some address ranges may not be available for certain
buffer sizes. Users should verify that the DMA base
address is compatible with the buffer size selected.
Figure 24-2 shows how the parts of the address define
the buffer locations in data memory. In this case, the
module “allocates” 256 bytes of data RAM (1000h to
1100h) for 32 buffers of four words each. However, this
is not a hard allocation and nothing prevents these
locations from being used for other purposes. For
example, in the current case, if Analog Channels 1, 3
and 8 are being sampled and converted, conversion
data will only be written to the channel buffers, starting
at 1008h, 1018h and 1040h. The holes in the PIA buffer
space can be used for any other purpose. It is the
user’s responsibility to keep track of buffer locations
and prevent data overwrites.
 2016 Microchip Technology Inc.
DS30010118B-page 289