PIC24FJ64GA705 Datasheet, PDF (102/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 9-2: CLKDIV: CLOCK DIVIDER REGISTER
R/W-0
ROI
bit 15
R/W-0
DOZE2
R/W-1
DOZE1
R/W-1
DOZE0
R/W-0
DOZEN⁽¹⁾
R/W-0
R/W-0
R/W-0
U-0
U-0
CPDIV1
CPDIV0
PLLEN
—
—
bit 7
R/W-0
RCDIV2
U-0
—
R/W-0
RCDIV1
U-0
—
R/W-0
RCDIV0
bit 8
U-0
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14-12
bit 11
bit 10-8
bit 7-6
bit 5
bit 4-0
ROI: Recover on Interrupt bit
1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1
0 = Interrupts have no effect on the DOZEN bit
DOZE<2:0>: CPU Peripheral Clock Ratio Select bits
111 = 1:128
110 = 1:64
101 = 1:32
100 = 1:16
011 = 1:8 (default)
010 = 1:4
001 = 1:2
000 = 1:1
DOZEN: Doze Enable bit⁽¹⁾
1 = DOZE<2:0> bits specify the CPU peripheral clock ratio
0 = CPU peripheral clock ratio is set to 1:1
RCDIV<2:0>: System Frequency Divider Clock Source Select bits
111 = Reserved; do not use
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator (XT, HS, EC) with PLL module (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator (FRC) with PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
CPDIV<1:0>: System Clock Select bits (postscaler select from PLL, 32 MHz clock branch)
11 = 4 MHz (divide-by-8)
10 = 8 MHz (divide-by-4)
01 = 16 MHz (divide-by-2)
00 = 32 MHz (divide-by-1)
PLLEN: PLL Enable bit
1 = PLL is always active
0 = PLL is only active when a PLL Oscillator mode is selected (OSCCON<14:12> = 011 or 001)
Unimplemented: Read as ‘0’
Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.
DS30010118B-page 102
 2016 Microchip Technology Inc.