PIC24FJ64GA705 Datasheet, PDF (226/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 18-2: I2CxCONH: I2Cx CONTROL REGISTER HIGH
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
—
bit 7
R/W-0
PCIE
R/W-0
SCIE
R/W-0
BOEN
R/W-0
SDAHT⁽¹⁾
R/W-0
SBCDE
R/W-0
AHEN
R/W-0
DHEN
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
PCIE: Stop Condition Interrupt Enable bit (I²C Slave mode only)
1 = Enables interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled
SCIE: Start Condition Interrupt Enable bit (I²C Slave mode only)
1 = Enables interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled
BOEN: Buffer Overwrite Enable bit (I²C Slave mode only)
1 = I2CxRCV is updated and an ACK is generated for a received address/data byte, ignoring the state
of the I2COV bit only if RBF bit = 0
0 = I2CxRCV is only updated when I2COV is clear
SDAHT: SDAx Hold Time Selection bit⁽¹⁾
1 = Minimum of 300 ns hold time on SDAx after the falling edge of SCLx
0 = Minimum of 100 ns hold time on SDAx after the falling edge of SCLx
SBCDE: Slave Mode Bus Collision Detect Enable bit (I²C Slave mode only)
If, on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the
BCL bit is set and the bus goes Idle. This Detection mode is only valid during data and ACK transmit
sequences.
1 = Enables slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
AHEN: Address Hold Enable bit (I²C Slave mode only)
1 = Following the 8th falling edge of SCLx for a matching received address byte; SCLREL bit
(I2CxCONL<12>) will be cleared and SCLx will be held low
0 = Address holding is disabled
DHEN: Data Hold Enable bit (I²C Slave mode only)
1 = Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the SCLREL
bit (I2CxCONL<12>) and SCLx is held low
0 = Data holding is disabled
Note 1: This bit must be set to ‘0’ for 1 MHz operation.
DS30010118B-page 226
 2016 Microchip Technology Inc.