PIC24FJ64GA705 Datasheet, PDF (257/412 Pages) –

PIC24FJ256GA705 FAMILY
21.3.2 RTCVAL REGISTER MAPPINGS
REGISTER 21-4: RTCCON2H: RTCC CONTROL REGISTER 2 (HIGH)⁽¹⁾
R/W-0
bit 15
R/W-0
R/W-1
R/W-1
R/W-1
DIV<15:8>
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
bit 7
R/W-1
R/W-1
R/W-1
R/W-1
DIV<7:0>
R/W-1
R/W-1
R/W-1
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
DIV<15:0>: Clock Divide bits
Sets the period of the clock divider counter; value should cause a nominal 1/2 second underflow.
Note 1: A write to this register is only allowed when WRLOCK = 1.
 2016 Microchip Technology Inc.
DS30010118B-page 257