PIC24FJ64GA705 Datasheet, PDF (190/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 16-1: CCPxCON1L: CCPx CONTROL 1 LOW REGISTERS
R/W-0
CCPON
bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
CCPSIDL CCPSLP TMRSYNC CLKSEL2
R/W-0
CLKSEL1
R/W-0
CLKSEL0
bit 8
R/W-0
TMRPS1
bit 7
R/W-0
TMRPS0
R/W-0
T32
R/W-0
CCSEL
R/W-0
MOD3
R/W-0
MOD2
R/W-0
MOD1
R/W-0
MOD0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10-8
bit 7-6
bit 5
bit 4
CCPON: CCPx Module Enable bit
1 = Module is enabled with an operating mode specified by the MOD<3:0> control bits
0 = Module is disabled
Unimplemented: Read as ‘0’
CCPSIDL: CCPx Stop in Idle Mode Bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
CCPSLP: CCPx Sleep Mode Enable bit
1 = Module continues to operate in Sleep modes
0 = Module does not operate in Sleep modes
TMRSYNC: Time Base Clock Synchronization bit
1 = Module time base clock is synchronized to the internal system clocks; timing restrictions apply
0 = Module time base clock is not synchronized to the internal system clocks
CLKSEL<2:0>: CCPx Time Base Clock Select bits
111 = TCKIA pin
110 = TCKIB pin
101 = PLL clock
100 = 2x peripheral clock
010 = SOSC clock
001 = Reference clock output
000 = System clock
For MCCP1:
011 = CLC1 output
For MCCP2:
011 = CLC2 output
TMRPS<1:0>: Time Base Prescale Select bits
11 = 1:64 Prescaler
10 = 1:16 Prescaler
01 = 1:4 Prescaler
00 = 1:1 Prescaler
T32: 32-Bit Time Base Select bit
1 = Uses 32-bit time base for timer, single edge output compare or input capture function
0 = Uses 16-bit time base for timer, single edge output compare or input capture function
CCSEL: Capture/Compare Mode Select bit
1 = Input capture peripheral
0 = Output compare/PWM/timer peripheral (exact function is selected by the MOD<3:0> bits)
DS30010118B-page 190
 2016 Microchip Technology Inc.