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PIC24FJ64GA705 Datasheet, PDF (163/412 Pages) –
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PIC24FJ256GA705 FAMILY
FIGURE 13-2:
TIMER2 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
T2CK
TxCK
SOSC Input
LPRC Input
TCY
Gate
Sync
TON
TGATE
TECS<1:0>
Set T2IF
1
0
Reset
QD
Q CK
TMR2
TGATE(1)
TCS(1)
Sync
TCKPS<1:0>
2
Prescaler
1, 8, 64, 256
Equal
Comparator
PR2
Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.5 “Peripheral
Pin Select (PPS)” for more information.
FIGURE 13-3:
TIMER3 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM
T3CK
TxCK
SOSC Input
LPRC Input
TCY
Gate
Sync
TON
TCKPS<1:0>
2
Prescaler
1, 8, 64, 256
TGATE
TECS<1:0>
1
Set T3IF
0
Reset
QD
Q CK
TMR3
TGATE(1)
TCS(1)
A/D Event Trigger(2)
Equal
Comparator
PR3
Note 1:
2:
The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.5 “Peripheral
Pin Select (PPS)” for more information.
The A/D event trigger is available only on Timer3.
 2016 Microchip Technology Inc.
DS30010118B-page 163
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