PIC24FJ64GA705 Datasheet, PDF (180/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2
R/W-0
FLTMD
bit 15
R/W-0
FLTOUT
R/W-0
FLTTRIEN
R/W-0
OCINV
U-0
R/W-0
R/W-0
—
DCB1⁽³⁾
DCB0⁽³⁾
R/W-0
OC32
bit 8
R/W-0
OCTRIG
bit 7
R/W-0, HS
TRIGSTAT
R/W-0
OCTRIS
R/W-0
SYNCSEL4
R/W-1
SYNCSEL3
R/W-1
SYNCSEL2
R/W-0
SYNCSEL1
R/W-0
SYNCSEL0
bit 0
Legend:
R = Readable bit
-n = Value at POR
HS = Hardware Settable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10-9
bit 8
bit 7
bit 6
bit 5
FLTMD: Fault Mode Select bit
1 = Fault mode is maintained until the Fault source is removed and the corresponding OCFLT0 bit is
cleared in software
0 = Fault mode is maintained until the Fault source is removed and a new PWM period starts
FLTOUT: Fault Out bit
1 = PWM output is driven high on a Fault
0 = PWM output is driven low on a Fault
FLTTRIEN: Fault Output State Select bit
1 = Pin is forced to an output on a Fault condition
0 = Pin I/O condition is unaffected by a Fault
OCINV: OCMP Invert bit
1 = OCx output is inverted
0 = OCx output is not inverted
Unimplemented: Read as ‘0’
DCB<1:0>: PWM Duty Cycle Least Significant bits⁽³⁾
11 = Delays OCx falling edge by ¾ of the instruction cycle
10 = Delays OCx falling edge by ½ of the instruction cycle
01 = Delays OCx falling edge by ¼ of the instruction cycle
00 = OCx falling edge occurs at the start of the instruction cycle
OC32: Cascade Two OC Modules Enable bit (32-bit operation)
1 = Cascade module operation is enabled
0 = Cascade module operation is disabled
OCTRIG: OCx Trigger/Sync Select bit
1 = Triggers OCx from the source designated by the SYNCSELx bits
0 = Synchronizes OCx with the source designated by the SYNCSELx bits
TRIGSTAT: Timer Trigger Status bit
1 = Timer source has been triggered and is running
0 = Timer source has not been triggered and is being held clear
OCTRIS: OCx Output Pin Direction Select bit
1 = OCx pin is tri-stated
0 = Output Compare Peripheral x is connected to an OCx pin
Note 1:
2:
3:
Never use an Output Compare x module as its own Trigger source, either by selecting this mode or
another equivalent SYNCSELx setting.
Use these inputs as Trigger sources only and never as Sync sources.
The DCB<1:0> bits are double-buffered in the PWM modes only (OCM<2:0> (OCxCON1<2:0>) = 111, 110).
DS30010118B-page 180
 2016 Microchip Technology Inc.