PIC24FJ64GA705 Datasheet, PDF (325/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 27-3: CTMUCON2L: CTMU CONTROL REGISTER 2 LOW
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
bit 15
U-0
U-0
U-0
R/W-0
U-0
R/W-0
—
—
—
IRSTEN
—
DSCHS2
bit 7
U-0
—
R/W-0
DSCHS1
U-0
—
bit 8
R/W-0
DSCHS0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-5
bit 4
bit 3
bit 2-0
Unimplemented: Read as ‘0’
IRSTEN: CTMU Current Source Reset Enable bit
1 = Signal selected by DSCHS<2:0> bits or IDISSEN control bit will reset CTMU edge detect logic
0 = CTMU edge detect logic will not occur
Unimplemented: Read as ‘0’
DSCHS<2:0>: Discharge Source Select Bits
111 = CLC2 out
110 = CLC1 out
101 = Disabled
100 = A/D end of conversion
011 = MCCP3 auxiliary output
010 = MCCP2 auxiliary output
001 = MCCP1 auxiliary output
000 = Disabled
 2016 Microchip Technology Inc.
DS30010118B-page 325