PIC24FJ64GA705 Datasheet, PDF (63/412 Pages) –

PIC24FJ256GA705 FAMILY
5.0 DIRECT MEMORY ACCESS
CONTROLLER (DMA)
Note:
This data sheet summarizes the features
of the PIC24FJ256GA705 family of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
the “dsPIC33/PIC24 Family Reference
Manual”, “Direct Memory Access
Controller (DMA)” (DS39742), which is
available from the Microchip web site
(www.microchip.com). The information in
this data sheet supersedes the information
in the FRM.
The Direct Memory Access (DMA) Controller is designed
to service high throughput data peripherals operating on
the SFR bus, allowing them to access data memory
directly and alleviating the need for CPU intensive man-
agement. By allowing these data intensive peripherals to
share their own data path, the main data bus is also
deloaded, resulting in additional power savings.
The DMA Controller functions both as a peripheral and a
direct extension of the CPU. It is located on the microcon-
troller data bus between the CPU and DMA-enabled
peripherals, with direct access to SRAM. This partitions
the SFR bus into two buses, allowing the DMA Controller
access to the DMA capable peripherals located on the
new DMA SFR bus. The controller serves as a master
device on the DMA SFR bus, controlling data flow from
DMA capable peripherals.
The controller also monitors CPU instruction process-
ing directly, allowing it to be aware of when the CPU
requires access to peripherals on the DMA bus and
automatically relinquishing control to the CPU as
needed. This increases the effective bandwidth for
handling data without DMA operations causing a
processor stall. This makes the controller essentially
transparent to the user.
The DMA Controller has these features:
• Six Multiple Independent and Independently
Programmable Channels
• Concurrent Operation with the CPU (no DMA
caused Wait states)
• DMA Bus Arbitration
• Five Programmable Address modes
• Four Programmable Transfer modes
• Four Flexible Internal Data Transfer modes
• Byte or Word Support for Data Transfer
• 16-Bit Source and Destination Address Register
for Each Channel, Dynamically Updated and
Reloadable
• 16-Bit Transaction Count Register, Dynamically
Updated and Reloadable
• Upper and Lower Address Limit Registers
• Counter Half-Full Level Interrupt
• Software Triggered Transfer
• Null Write mode for Symmetric Buffer Operations
A simplified block diagram of the DMA Controller is
shown in Figure 5-1.
FIGURE 5-1:
DMA FUNCTIONAL BLOCK DIAGRAM
To I/O Ports
and Peripherals
CPU Execution Monitoring
To DMA-Enabled
Peripherals
Data
Bus
Control
Logic
DMACON
DMAH
DMAL
DMABUF
DMACH0
DMAINT0
DMASRC0
DMADST0
DMACNT0
Channel 0
DMACH1
DMAINT1
DMASRC1
DMADST1
DMACNT1
Channel 1
DMACH4
DMAINT4
DMASRC4
DMADST4
DMACNT4
Channel 4
DMACH5
DMAINT5
DMASRC5
DMADST5
DMACNT5
Channel 5
Data RAM
Data RAM
Address Generation
 2016 Microchip Technology Inc.
DS30010118B-page 63