PIC24FJ64GA705 Datasheet, PDF (166/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 13-2: TyCON: TIMER3 CONTROL REGISTER⁽¹⁾
R/W-0
U-0
R/W-0
U-0
U-0
TON⁽²⁾
—
TSIDL⁽²⁾
—
—
bit 15
U-0
R/W-0
R/W-0
—
TECS1^(2,3) TECS0^(2,3)
bit 8
U-0
—
bit 7
R/W-0
R/W-0
R/W-0
U-0
TGATE⁽²⁾ TCKPS1⁽²⁾ TCKPS0⁽²⁾
—
U-0
R/W-0
U-0
—
TCS^(2,3)
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12-10
bit 9-8
bit 7
bit 6
bit 5-4
bit 3-2
bit 1
bit 0
TON: Timery On bit⁽²⁾
1 = Starts 16-bit Timery
0 = Stops 16-bit Timery
Unimplemented: Read as ‘0’
TSIDL: Timery Stop in Idle Mode bit⁽²⁾
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
Unimplemented: Read as ‘0’
TECS<1:0>: Timery Extended Clock Source Select bits (selected when TCS = 1)^(2,3)
11 = Generic timer (TxCK) external input
10 = LPRC Oscillator
01 = TyCK external clock input
00 = SOSC
Unimplemented: Read as ‘0’
TGATE: Timery Gated Time Accumulation Enable bit⁽²⁾
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
TCKPS<1:0>: Timery Input Clock Prescale Select bits⁽²⁾
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
Unimplemented: Read as ‘0’
TCS: Timery Clock Source Select bit^(2,3)
1 = External clock from pin, TyCK (on the rising edge)
0 = Internal clock (FOSC/2)
Unimplemented: Read as ‘0’
Note 1:
2:
3:
Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.
When 32-bit operation is enabled (T2CON<3> = 1), this bit has no effect on Timery operation; all timer
functions are set through T2CON.
If TCS = 1 and TECS<1:0> = x1, the selected external timer input (TyCK) must be configured to an
available RPn/RPIn pin. For more information, see Section 11.5 “Peripheral Pin Select (PPS)”.
DS30010118B-page 166
 2016 Microchip Technology Inc.