PIC24FJ64GA705 Datasheet, PDF (72/412 Pages) –

PIC24FJ256GA705 FAMILY
6.2 RTSP Operation
The PIC24F Flash program memory array is organized
into rows of 128 instructions or 384 bytes. RTSP allows
the user to erase blocks of eight rows (1024 instruc-
tions) at a time and to program one row at a time. It is
also possible to program two instruction word blocks.
The 8-row erase blocks and single row write blocks are
edge-aligned, from the beginning of program memory, on
boundaries of 3072 bytes and 384 bytes, respectively.
When data is written to program memory using TBLWT
instructions, the data is not written directly to memory.
Instead, data written using Table Writes is stored in
holding latches until the programming sequence is
executed.
Any number of TBLWT instructions can be executed
and a write will be successfully performed. However,
128 TBLWT instructions are required to write the full row
of memory.
To ensure that no data is corrupted during a write, any
unused address should be programmed with
FFFFFFh. This is because the holding latches reset to
an unknown state, so if the addresses are left in the
Reset state, they may overwrite the locations on rows
which were not rewritten.
The basic sequence for RTSP programming is to set
the Table Pointer to point to the programming latches,
do a series of TBLWT instructions to load the buffers
and set the NVMADRU/NVMADR registers to point to
the destination. Programming is performed by setting
the control bits in the NVMCON register.
Data can be loaded in any order and the holding regis-
ters can be written to multiple times before performing
a write operation. Subsequent writes, however, will
wipe out any previous writes.
Note: Writing to a location multiple times without
erasing is not recommended.
All of the Table Write operations are single-word writes
(2 instruction cycles), because only the buffers are writ-
ten. A programming cycle is required for programming
each row.
6.3 JTAG Operation
The PIC24F family supports JTAG boundary scan.
Boundary scan can improve the manufacturing
process by verifying pin to PCB connectivity.
6.4 Enhanced In-Circuit Serial
Programming
Enhanced In-Circuit Serial Programming uses an on-
board bootloader, known as the Program Executive
(PE), to manage the programming process. Using an
SPI data frame format, the Program Executive can
erase, program and verify program memory. For more
information on Enhanced ICSP, see the device
programming specification.
6.5 Control Registers
There are four SFRs used to read and write the
program Flash memory: NVMCON, NVMADRU,
NVMADR and NVMKEY.
The NVMCON register (Register 6-1) controls which
blocks are to be erased, which memory type is to be
programmed and when the programming cycle starts.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user must consecutively write 55h and AAh to the
NVMKEY register. Refer to Section 6.6 “Programming
Operations” for further details.
The NVMADRU/NVMADR registers contain the upper
byte and lower word of the destination of the NVM write
or erase operation. Some operations (chip erase)
operate on fixed locations and do not require an address
value.
6.6 Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. During a programming or erase operation, the
processor stalls (waits) until the operation is finished.
Setting the WR bit (NVMCON<15>) starts the opera-
tion and the WR bit is automatically cleared when the
operation is finished.
DS30010118B-page 72
 2016 Microchip Technology Inc.