PIC24FJ64GA705 Datasheet, PDF (250/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 20-9: PADCON: PAD CONFIGURATION CONTROL REGISTER
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
IOCON
—
—
—
—
—
—
bit 15
U-0
—
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
PMPTTL
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14-1
bit 0
IOCON: Used for Non-PMP functionality
Unimplemented: Read as ‘0’
PMPTTL: EPMP Module TTL Input Buffer Select bit
1 = EPMP module inputs (PMDx, PMCS1) use TTL input buffers
0 = EPMP module inputs use Schmitt Trigger input buffers
DS30010118B-page 250
 2016 Microchip Technology Inc.