PIC24FJ64GA705 Datasheet, PDF (121/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 10-5: PMD5: PERIPHERAL MODULE DISABLE REGISTER 5
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
bit 15
U-0
—
bit 8
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
CCP4MD CCP3MD CCP2MD CCP1MD
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
CCP4MD: MCCP4 Module Disable bit
1 = Module is disabled
0 = Module power and clock sources are enabled
CCP3MD: MCCP3 Module Disable bit
1 = Module is disabled
0 = Module power and clock sources are enabled
CCP2MD: MCCP2 Module Disable bit
1 = Module is disabled
0 = Module power and clock sources are enabled
CCP1MD: MCCP1 Module Disable bit
1 = Module is disabled
0 = Module power and clock sources are enabled
 2016 Microchip Technology Inc.
DS30010118B-page 121