PIC24FJ64GA705 Datasheet, PDF (100/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER⁽¹⁾
U-0
R-x⁽²⁾
R-x⁽²⁾
R-x⁽²⁾
U-0
R/W-x⁽²⁾
—
COSC2
COSC1
COSC0
—
NOSC2
bit 15
R/W-x⁽²⁾
NOSC1
R/W-x⁽²⁾
NOSC0
bit 8
R/W-0
CLKLOCK
bit 7
R/W-0
IOLOCK⁽³⁾
R-0⁽⁴⁾
LOCK
U-0
R/CO-0
R/W-0
R/W-0
R/W-0
—
CF
POSCEN SOSCEN
OSWEN
bit 0
Legend:
R = Readable bit
-n = Value at POR
CO = Clearable Only bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14-12
bit 11
bit 10-8
bit 7
bit 6
bit 5
Unimplemented: Read as ‘0’
COSC<2:0>: Current Oscillator Selection bits⁽²⁾
111 = Oscillator with Frequency Divider (OSCFDIV)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
Unimplemented: Read as ‘0’
NOSC<2:0>: New Oscillator Selection bits⁽²⁾
111 = Oscillator with Frequency Divider (OSCFDIV)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
CLKLOCK: Clock Selection Lock Enable bit
If FSCM is Enabled (FCKSM<1:0> = 00):
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit
If FSCM is Disabled (FCKSM<1:0> = 1x):
Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
IOLOCK: I/O Lock Enable bit⁽³⁾
1 = I/O lock is active
0 = I/O lock is not active
LOCK: PLL Lock Status bit⁽⁴⁾
1 = PLL module is in lock or PLL module start-up timer is satisfied
0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled
Note 1:
2:
3:
4:
OSCCON is protected by a write lock to prevent inadvertent clock switches. See Section 9.4 “Clock
Switching Operation” for more information.
Reset values for these bits are determined by the FNOSCx Configuration bits.
The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In
addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared.
This bit also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.
DS30010118B-page 100
 2016 Microchip Technology Inc.