PIC24FJ64GA705 Datasheet, PDF (119/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 10-3: PMD3: PERIPHERAL MODULE DISABLE REGISTER 3
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
CMPMD
bit 15
R/W-0
RTCCMD
R/W-0
PMPMD
bit 8
R/W-0
U-0
U-0
U-0
U-0
U-0
R/W-0
U-0
CRCMD
—
—
—
—
—
I2C2MD
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-11
bit 10
bit 9
bit 8
bit 7
bit 6-2
bit 1
bit 0
Unimplemented: Read as ‘0’
CMPMD: Triple Comparator Module Disable bit
1 = Module is disabled
0 = Module power and clock sources are enabled
RTCCMD: RTCC Module Disable bit
1 = Module is disabled
0 = Module power and clock sources are enabled
PMPMD: Enhanced Parallel Master Port Disable bit
1 = Module is disabled
0 = Module power and clock sources are enabled
CRCMD: CRC Module Disable bit
1 = Module is disabled
0 = Module power and clock sources are enabled
Unimplemented: Read as ‘0’
I2C2MD: I2C2 Module Disable bit
1 = Module is disabled
0 = Module power and clock sources are enabled
Unimplemented: Read as ‘0’
 2016 Microchip Technology Inc.
DS30010118B-page 119