PIC24FJ64GA705 Datasheet, PDF (19/412 Pages) –

PIC24FJ256GA705 FAMILY
FIGURE 1-1:
PIC24FJ256GA705 FAMILY GENERAL BLOCK DIAGRAM
Interrupt
Controller
EDS and
Table Data
Access Control
23
23
8
16
PCH
PCL
Program Counter
Stack
Control
Logic
Repeat
Control
Logic
Data Bus
16
16
Data Latch
Data RAM
Address
Latch
16
Address Latch
Program Memory/
Extended Data
Space
Data Latch
Address Bus
24
Read AGU
Write AGU
EA MUX
Inst Latch
16
16
Literal
Data
Inst Register
DMA
Controller
16
16
Control Signals
OSCO/CLKO
OSCI/CLKI
Timing
Generation
REFO
FRC/LPRC
Oscillators
Precision
Band Gap
Reference
Voltage
Regulators
Instruction
Decode and
Control
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
HLVD &
BOR⁽²⁾
Divide
Support
17x17
Multiplier
DMA
Data Bus
16 x 16
W Reg Array
16-Bit ALU
16
PORTA⁽¹⁾
(12 I/Os)
PORTB
(16 I/Os)
PORTC⁽¹⁾
(8 I/Os)
16
VCAP
VDD, VSS MCLR
MCCP1/2/3 Timer1 Timer2/3⁽³⁾
RTCC
12-Bit
A/D
Comparators⁽³⁾
CLC1-2⁽¹⁾
EPMP/PSP
IC
1-3⁽³⁾
OC/PWM
1-3⁽³⁾
IOCs⁽¹⁾
SPI
1-3⁽³⁾
I2C1-2
UART
1-2⁽³⁾
CTMU
Note 1: Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-3 for specific implementations by pin count.
2: BOR functionality is provided when the on-board voltage regulator is enabled.
3: Some peripheral I/Os are only accessible through remappable pins.
 2016 Microchip Technology Inc.
DS30010118B-page 19