PIC24FJ64GA705 Datasheet, PDF (188/412 Pages) –

PIC24FJ256GA705 FAMILY
16.4 Input Capture Mode
Input Capture mode is used to capture a timer value
from an independent timer base upon an event on an
input pin or other internal Trigger source. The input
capture features are useful in applications requiring
frequency (time period) and pulse measurement.
Figure 16-6 depicts a simplified block diagram of the
Input Capture mode.
TABLE 16-3: INPUT CAPTURE MODES
MOD<3:0>
T32
(CCPxCON1L<3:0>) (CCPxCON1L<5>)
0000
0
0000
1
0001
0
0001
1
0010
0
0010
1
0011
0
0011
1
0100
0
0100
1
0101
0
0101
1
Input Capture mode uses a dedicated 16/32-bit, synchro-
nous, up counting timer for the capture function. The timer
value is written to the FIFO when a capture event occurs.
The internal value may be read (with a synchronization
delay) using the CCPxTMRH/L registers.
To use Input Capture mode, the CCSEL bit
(CCPxCON1L<4>) must be set. The T32 and
MOD<3:0> bits are used to select the proper Capture
mode, as shown in Table 16-3.
Operating Mode
Edge Detect (16-bit capture)
Edge Detect (32-bit capture)
Every Rising (16-bit capture)
Every Rising (32-bit capture)
Every Falling (16-bit capture)
Every Falling (32-bit capture)
Every Rise/Fall (16-bit capture)
Every Rise/Fall (32-bit capture)
Every 4th Rising (16-bit capture)
Every 4th Rising (32-bit capture)
Every 16th Rising (16-bit capture)
Every 16th Rising (32-bit capture)
FIGURE 16-6:
INPUT CAPTURE x BLOCK DIAGRAM
ICS<2:0>
MOD<3:0>
OPS<3:0>
ICx Clock
Sources
Clock
Select
Edge Detect Logic
and
Clock Synchronizer
Event and
Interrupt
Logic
Set CCPxIF
Increment
Reset
Trigger and
Sync Sources
Trigger and
Sync Logic
16
CCPxTMRH/L
4-Level FIFO Buffer
16
T32
16
CCPxBUFx
System Bus
DS30010118B-page 188
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