PIC24FJ64GA705 Datasheet, PDF (203/412 Pages) –

PIC24FJ256GA705 FAMILY
FIGURE 17-1:
SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)
Read
Internal
Data Bus
Write
SPIxRXB
SPIxTXB
SPIxURDT
MSB
SDIx
SDOx
SSx/FSYNC
SCKx
Receive
SPIxRXSR
SSx & FSYNC
Control
Shift
Control
Clock
Control
Edge
Select
Clock
Control
Transmit
SPIxTXSR
MSB
0
1
Edge
Select
Baud Rate
Generator
TXELM<5:0> = 6’b0
URDTEN
MCLKEN
MCLK
PBCLK
Enable Master Clock
17.3 Audio Mode Operation
To initialize the SPIx module for Audio mode, follow the
steps to initialize it for Master/Slave mode, but also set
the AUDEN bit (SPIxCON1H<15>). In Master+Audio
mode:
• This mode enables the device to generate SCKx
and LRC pulses as long as the SPIEN bit
(SPIxCON1L<15>) = 1.
• The SPIx module generates LRC and SCKx
continuously in all cases, regardless of the
transmit data, while in Master mode.
• The SPIx module drives the leading edge of LRC
and SCKx within 1 SCKx period, and the serial
data shifts in and out continuously, even when the
TX FIFO is empty.
In Slave+Audio mode:
• This mode enables the device to receive SCKx
and LRC pulses as long as the SPIEN bit
(SPIxCON1L<15>) = 1.
• The SPIx module drives zeros out of SDOx, but
does not shift data out or in (SDIx) until the
module receives the LRC (i.e., the edge that
precedes the left channel).
• Once the module receives the leading edge
of LRC, it starts receiving data if
DISSDI (SPIxCON1L<4>) = 0 and the serial data
shifts out continuously, even when the TX FIFO
is empty.
 2016 Microchip Technology Inc.
DS30010118B-page 203