PIC24FJ64GA705 Datasheet, PDF (183/412 Pages) –

PIC24FJ256GA705 FAMILY
16.0 CAPTURE/COMPARE/PWM/
TIMER MODULES (MCCP)
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is
not intended to be a comprehensive
reference source. For more information,
refer to the “dsPIC33/PIC24 Family Ref-
erence Manual”, “Capture/Compare/
PWM/Timer (MCCP and SCCP)”
(DS33035), which is available from the
Microchip web site (www.microchip.com).
The information in this data sheet
supersedes the information in the FRM.
PIC24FJ256GA705 family devices include several
Capture/Compare/PWM/Timer base modules, which
provide the functionality of three different peripherals of
earlier PIC24F devices. The module can operate in one
of three major modes:
• General Purpose Timer
• Input Capture
• Output Compare/PWM
This family of devices features 4 instances of the
MCCP module. MCCP1 provides up to six outputs and
an extended range of power control features, whereas
MCCP2-MCCP4 support two outputs.
The MCCPx modules can be operated only in one of
the three major modes at any time. The other modes
are not available unless the module is reconfigured for
the new mode.
A conceptual block diagram for the module is shown in
Figure 16-1. All three modules share a time base genera-
tor and a common Timer register pair (CCPxTMRH/L);
other shared hardware components are added as a
particular mode requires.
Each module has a total of 8 control and status registers:
• CCPxCON1L (Register 16-1)
• CCPxCON1H (Register 16-2)
• CCPxCON2L (Register 16-3)
• CCPxCON2H (Register 16-4)
• CCPxCON3L (Register 16-5)
• CCPxCON3H (Register 16-6)
• CCPxSTATL (Register 16-7)
• CCPxSTATH (Register 16-8)
Each module also includes 8 buffer/counter registers that
serve as Timer Value registers or data holding buffers:
• CCPxTMRH/CCPxTMRL (Timer High/Low
Counters)
• CCPxPRH/CCPxPRL (Timer Period High/Low)
• CCPxRAH/CCPxRAL (Primary Output Compare
Data Buffer)
• CCPxRBH/CCPxRBL (Secondary Output
Compare Data Buffer)
• CCPxBUFH/CCPxBUFL (Input Capture High/Low
Buffers)
FIGURE 16-1:
MCCPx CONCEPTUAL BLOCK DIAGRAM
External
Capture Input
Input Capture
CCPxIF
CCTxIF
Sync/Trigger Out
Special Trigger (to A/D)
Auxiliary Output (to CTMU)
Clock
Sources
Time Base
Generator
CCPxTMRH/L
T32
CCSEL
MOD<3:0>
Sync and
Gating
Sources
16/32-Bit
Timer
Output
Compare/PWM
Compare/PWM
Output(s)
OEFA/OEFB
 2016 Microchip Technology Inc.
DS30010118B-page 183