PIC24FJ64GA705 Datasheet, PDF (165/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 13-1: TxCON: TIMER2 CONTROL REGISTER⁽¹⁾ (CONTINUED)
bit 3
T32: 32-Bit Timer Mode Select bit⁽³⁾
1 = Timerx and Timery form a single 32-bit timer
0 = Timerx and Timery act as two 16-bit timers
In 32-bit mode, T3CON control bits do not affect 32-bit timer operation.
bit 2
Unimplemented: Read as ‘0’
bit 1
TCS: Timerx Clock Source Select bit⁽²⁾
1 = Timer source is selected by TECS<1:0>
0 = Internal clock (FOSC/2)
bit 0
Unimplemented: Read as ‘0’
Note 1:
2:
3:
Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.
If TCS = 1 and TECS<1:0> = x1, the selected external timer input (TxCK or TyCK) must be configured to
an available RPn/RPIn pin. For more information, see Section 11.5 “Peripheral Pin Select (PPS)”.
In 32-bit mode, the T3CON control bits do not affect 32-bit timer operation.
 2016 Microchip Technology Inc.
DS30010118B-page 165